參數(shù)資料
型號(hào)： CD74HCT7046AMTE4
廠商： TEXAS INSTRUMENTS INC
元件分類： XO, clock
英文描述： PHASE LOCKED LOOP, PDSO16
封裝： GREEN, PLASTIC, SOIC-16
文件頁數(shù)： 1/29頁
文件大?。?/td> 485K
代理商： CD74HCT7046AMTE4
1
Data sheet acquired from Harris Semiconductor
SCHS218C
Features
Center Frequency of 18MHz (Typ) at VCC = 5V,
Minimum Center Frequency of 12MHz at VCC = 4.5V
Choice of Two Phase Comparators
- Exclusive-OR
- Edge-Triggered JK Flip-Flop
Excellent VCO Frequency Linearity
VCO-Inhibit Control for ON/OFF Keying and for Low
Standby Power Consumption
Minimal Frequency Drift
Zero Voltage Offset Due to Op-Amp Buffer
Operating Power-Supply Voltage Range
- VCO Section . . . . . . . . . . . . . . . . . . . . . . . . . . 3V to 6V
- Digital Section . . . . . . . . . . . . . . . . . . . . . . . . 2V to 6V
Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
Wide Operating Temperature Range . . . -55oC to 125oC
Balanced Propagation Delay and Transition Times
Signicant Power Reduction Compared to LSTTL
Logic ICs
HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC
at VCC = 5V
HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
VIL= 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il ≤ 1A at VOL, VOH
Applications
FM Modulation and Demodulation
Frequency Synthesis and Multiplication
Frequency Discrimination
Tone Decoding
Data Synchronization and Conditioning
Voltage-to-Frequency Conversion
Motor-Speed Control
Related Literature
- AN8823, CMOS Phase-Locked-Loop Application
Using the CD74HC/HCT7046A and
CD74HC/HCT7046A
Description
The
CD74HC7046A
and
CD74HCT7046A
high-speed
silicon-gate CMOS devices, specied in compliance with
JEDEC Standard No. 7A, are phase-locked-loop (PLL)
circuits that contain a linear voltage-controlled oscillator
(VCO), two-phase comparators (PC1, PC2), and a lock
detector. A signal input and a comparator input are common
to each comparator. The lock detector gives a HIGH level at
pin 1 (LD) when the PLL is locked. The lock detector
capacitor must be connected between pin 15 (CLD) and pin
8 (Gnd). For a frequency range of 100kHz to 10MHz, the
lock
detector
capacitor
should
be
1000pF
to
10pF,
respectively.
The signal input can be directly coupled to large voltage
signals, or indirectly coupled (with a series capacitor) to
small voltage signals. A self-bias input circuit keeps small
voltage signals within the linear region of the input ampliers.
With a passive low-pass lter, the 7046A forms a second-
order loop PLL. The excellent VCO linearity is achieved by
the use of linear op-amp techniques.
Ordering Information
PART NUMBER
TEMP. RANGE
(oC)
PACKAGE
CD74HC7046AE
-55 to 125
16 Ld PDIP
CD74HC7046AM
-55 to 125
16 Ld SOIC
CD74HC7046AMT
-55 to 125
16 Ld SOIC
CD74HC7046AM96
-55 to 125
16 Ld SOIC
CD74HCT7046AE
-55 to 125
16 Ld PDIP
CD74HCT7046AM
-55 to 125
16 Ld SOIC
CD74HCT7046AMT
-55 to 125
16 Ld SOIC
CD74HCT7046AM96
-55 to 125
16 Ld SOIC
NOTE: When ordering, use the entire part number. The sufx 96
denotes tape and reel. The sufx T denotes a small-quantity reel
of 250.
February 1998 - Revised October 2003
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
2003, Texas Instruments Incorporated
0.1
CD74HC7046A,
CD74HCT7046A
Phase-Locked Loop
with VCO and Lock Detector
[ /Title
(CD74
HC704
6A,
CD74
HCT70
46A)
/Sub-
ject
(Phase-
Locked
Loop
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