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參數(shù)資料
| 型號(hào)： | CD74HCT7046AM |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | XO, clock |
| 英文描述： | PHASE LOCKED LOOP, PDSO16 |
| 封裝： | GREEN, PLASTIC, SOIC-16 |
| 文件頁數(shù)： | 23/29頁 |
| 文件大?。?/td> | 485K |
| 代理商： | CD74HCT7046AM |
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General Description
VCO
The VCO requires one external capacitor C1 (between C1A
and C1B) and one external resistor R1 (between R1 and
Gnd) or two external resistors R1 and R2 (between R1 and
Gnd, and R2 and Gnd). Resistor R1 and capacitor C1 deter-
mine the frequency range of the VCO. Resistor R2 enables
the VCO to have a frequency offset if required. See logic dia-
gram, Figure 1.
The high input impedance of the VCO simplies the design
of low-pass lters by giving the designer a wide choice of
resistor/capacitor ranges. In order not to load the low-pass
lter, a demodulator output of the VCO input voltage is pro-
vided at pin 10 (DEMOUT). In contrast to conventional tech-
niques where the DEMOUT voltage is one threshold voltage
lower than the VCO input voltage, here the DEMOUT voltage
equals that of the VCO input. If DEMOUT is used, a load
resistor (RS) should be connected from DEMOUT to Gnd; if
unused, DEMOUT should be left open. The VCO output
(VCOOUT) can be connected directly to the comparator
input (COMPIN), or connected via a frequency-divider. The
VCO output signal has a specied duty factor of 50%. A
LOW level at the inhibit input (INH) enables the VCO, while a
HIGH level disables the VCO to minimize standby power
consumption.
Phase Comparators
The signal input (SIGIN) can be directly coupled to the self-
biasing amplier at pin 14, provided that the signal swing is
between the standard HC family input logic levels, Capaci-
tive coupling is required for signals with smaller swings.
Phase Comparator 1 (PC1)
This is an Exclusive-OR network. The signal and comparator
input frequencies (fi) must have a 50% duty factor to obtain
the maximum locking range. The transfer characteristic of
PC1, assuming ripple (fr = 2fi) is suppressed, is:
VDEMOUT =(VCC/π)(φSIGIN - φCOMPIN) where VDEMOUT
is the demodulator output at pin 10; VDEMOUT =VPC1OUT
(via low-pass lter).
The average output voltage from PC1, fed to the VCO input
via the low-pass lter and seen at the demodulator output at
pin 10 (VDEMOUT), is the resultant of the phase differences
of signals (SIGIN) and the comparator input (COMPIN)as
shown in Figure 2. The average of VDEM is equal to 1/2 VCC
when there is no signal or noise at SIGIN, and with this input
the VCO oscillates at the center frequency (fo). Typical wave-
forms for the PC1 loop locked at fo shown in Figure 3.
The frequency capture range (2fc) is dened as the fre-
quency range of input signals on which the PLL will lock if it
was initially out-of-lock. The frequency lock range (2fL)is
dened as the frequency range of input signals on which the
loop will stay locked if it was initially in lock. The capture
range is smaller or equal to the lock range.
With PC1, the capture range depends on the low-pass lter
characteristics and can be made as large as the lock range.
This conguration retains lock behavior even with very noisy
input signals. Typical of this type of phase comparator is that
it can lock to input frequencies close to the harmonics of the
VCO center frequency.
Phase Comparator 2 (PC2)
This is a positive edge-triggered phase and frequency detec-
tor. When the PLL is using this comparator, the loop is con-
trolled by positive signal transitions and the duty factors of
SIGIN and COMPIN are not important. PC2 comprises two
D-type ip-ops, control-gating and a three-state output
stage. The circuit functions as an up-down counter (Figure
1) where SIGIN causes an up-count and COMPIN a down-
count. The transfer function of PC2, assuming ripple (fr =fi)
is suppressed, is:
VDEMOUT =(VCC/4π)(φSIGN - φCOMPIN) where VDEMOUT
is the demodulator output at pin 10; VDEMOUT =VPC2OUT
(via low-pass lter).
The average output voltage from PC2, fed to the VCO via the
low-pass lter and seen at the demodulator output at pin 10
(VDEMOUT), is the resultant of the phase differences of
SIGIN and COMPIN as shown in Figure 4. Typical waveforms
for the PC2 loop locked at fo are shown in Figure 5.
When the frequencies of SIGIN and COMPIN are equal but
the phase of SIGIN leads that of COMPIN, the p-type output
driver at PC2OUT is held “ON” for a time corresponding to
the phase differences (
φDEMOUT). When the phase of SIGIN
lags that of COMPIN, the n-type driver is held “ON”.
When the frequency of SIGIN is higher than that of COMPIN,
the p-type output driver is held “ON” for most of the input sig-
nal cycle time, and for the remainder of the cycle both n-type
and p-type drivers are “OFF” (three-state). If the SIGIN fre-
Pin Descriptions
PIN NO.
SYMBOL
NAME AND FUNCTION
1
LD
Lock Detector Output (Active High)
2
PC1OUT
Phase Comparator 1 Output
3
COMPIN
Comparator Input
4
VCOOUT
VCO Output
5
INH
Inhibit Input
6C1A
Capacitor C1 Connection A
7C1B
Capacitor C1 Connection B
8
Gnd
Ground (0V)
9
VCOIN
VCO Input
10
DEMOUT
Demodulator Output
11
R1
Resistor R1 Connection
12
R2
Resistor R2 Connection
13
PC2OUT
Phase Comparator 2 Output
14
SIGIN
Signal Input
15
CLD
Lock Detector Capacitor Input
16
VCC
Positive Supply Voltage
CD74HC7046A, CD74HCT7046A
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