參數(shù)資料
型號(hào)： CD74HCT4046AMTE4
廠商： TEXAS INSTRUMENTS INC
元件分類： XO, clock
英文描述： PHASE LOCKED LOOP, 38 MHz, PDSO16
封裝： GREEN, PLASTIC, MS-012AC, SOIC-16
文件頁數(shù)： 1/32頁
文件大小： 687K
代理商： CD74HCT4046AMTE4
1
Data sheet acquired from Harris Semiconductor
SCHS204J
Features
Operating Frequency Range
- Up to 18MHz (Typ) at VCC = 5V
- Minimum Center Frequency of 12MHz at VCC = 4.5V
Choice of Three Phase Comparators
- EXCLUSIVE-OR
- Edge-Triggered JK Flip-Flop
- Edge-Triggered RS Flip-Flop
Excellent VCO Frequency Linearity
VCO-Inhibit Control for ON/OFF Keying and for Low
Standby Power Consumption
Minimal Frequency Drift
Operating Power Supply Voltage Range
- VCO Section . . . . . . . . . . . . . . . . . . . . . . . . . . 3V to 6V
- Digital Section . . . . . . . . . . . . . . . . . . . . . . . . 2V to 6V
Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
Wide Operating Temperature Range . . . -55oC to 125oC
Balanced Propagation Delay and Transition Times
Signicant Power Reduction Compared to LSTTL
Logic ICs
HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC
at VCC = 5V
HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
VIL= 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il ≤ 1A at VOL, VOH
Applications
FM Modulation and Demodulation
Frequency Synthesis and Multiplication
Frequency Discrimination
Tone Decoding
Data Synchronization and Conditioning
Voltage-to-Frequency Conversion
Motor-Speed Control
Description
The ’HC4046A and ’HCT4046A are high-speed silicon-gate
CMOS devices that are pin compatible with the CD4046B of
the “4000B” series. They are specified in compliance with
JEDEC standard number 7.
The ’HC4046A and ’HCT4046A are phase-locked-loop
circuits that contain a linear voltage-controlled oscillator
(VCO) and three different phase comparators (PC1, PC2 and
PC3). A signal input and a comparator input are common to
each comparator.
The signal input can be directly coupled to large voltage
signals, or indirectly coupled (with a series capacitor) to small
voltage signals. A self-bias input circuit keeps small voltage
signals within the linear region of the input amplifiers. With a
passive low-pass filter, the 4046A forms a second-order loop
PLL. The excellent VCO linearity is achieved by the use of
linear op-amp techniques.
Ordering Information
PART NUMBER
TEMP. RANGE
(oC)
PACKAGE
CD54HC4046AF3A
-55 to 125
16 Ld CERDIP
CD54HCT4046AF3A
-55 to 125
16 Ld CERDIP
CD74HC4046AE
-55 to 125
16 Ld PDIP
CD74HC4046AM
-55 to 125
16 Ld SOIC
CD74HC4046AMT
-55 to 125
16 Ld SOIC
CD74HC4046AM96
-55 to 125
16 Ld SOIC
CD74HC4046ANSR
-55 to 125
16 Ld SOP
CD74HC4046APWR
-55 to 125
16 Ld TSSOP
CD74HC4046APWT
-55 to 125
16 Ld TSSOP
CD74HCT4046AE
-55 to 125
16 Ld PDIP
CD74HCT4046AM
-55 to 125
16 Ld SOIC
CD74HCT4046AMT
-55 to 125
16 Ld SOIC
CD74HCT4046AM96
-55 to 125
16 Ld SOIC
NOTE: When ordering, use the entire part number. The sufxes 96
and R denote tape and reel. The sufx T denotes a small-quantity
reel of 250.
February 1998 - Revised December 2003
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
2003, Texas Instruments Incorporated
CD54HC4046A, CD74HC4046A,
CD54HCT4046A, CD74HCT4046A
High-Speed CMOS Logic
Phase-Locked Loop with VCO
[ /Title
(CD74
HC404
6A,
CD74
HCT40
46A)
/Sub-
ject
(High-
Speed
CMOS
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