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參數(shù)資料
| 型號(hào)： | CD74HC4040NSRE4 |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 通用總線功能 |
| 英文描述： | High-Speed CMOS Logic 12-Stage Binary Counter |
| 中文描述： | 高速CMOS邏輯12位的二進(jìn)制計(jì)數(shù)器 |
| 文件頁數(shù)： | 1/15頁 |
| 文件大?。?/td> | 346K |
| 代理商： | CD74HC4040NSRE4 |
1
Data sheet acquired from Harris Semiconductor
SCHS203D
Features
Fully Static Operation
Buffered Inputs
Common Reset
Negative Edge Pulsing
Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
Wide Operating Temperature Range . . . -55
o
C to 125
o
C
Balanced Propagation Delay and Transition Times
Significant Power Reduction Compared to LSTTL
Logic ICs
HC Types
- 2V to 6V Operation
- High Noise Immunity: N
IL
= 30%, N
IH
= 30% of V
CC
at V
CC
= 5V
HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V
IL
= 0.8V (Max), V
IH
= 2V (Min)
- CMOS Input Compatibility, I
l
≤
1
μ
A at V
OL
, V
OH
Description
The ’HC4040 and ’HCT4040 are 14-stage ripple-carry
binary counters. All counter stages are master-slave flip-
flops. The state of the stage advances one count on the
negative clock transition of each input pulse; a high voltage
level on the MR line resets all counters to their zero state. All
inputs and outputs are buffered.
Pinout
CD54HC4040, CD54HCT4040
(CERDIP)
CD74HC4040
(PDIP, SOIC, SOP)
CD74HCT4040
(PDIP, SOIC)
TOP VIEW
Ordering Information
PART NUMBER
TEMP. RANGE
(
o
C)
PACKAGE
CD54HC4040F3A
-55 to 125
16 Ld CERDIP
CD54HCT4040F3A
-55 to 125
16 Ld CERDIP
CD74HC4040E
-55 to 125
16 Ld PDIP
CD74HC4040M
-55 to 125
16 Ld SOIC
CD74HC4040MT
-55 to 125
16 Ld SOIC
CD74HC4040M96
-55 to 125
16 Ld SOIC
CD74HC4040NSR
-55 to 125
16 Ld SOP
CD74HCT4040E
-55 to 125
16 Ld PDIP
CD74HCT4040M
-55 to 125
16 Ld SOIC
CD74HCT4040MT
-55 to 125
16 Ld SOIC
CD74HCT4040M96
-55 to 125
16 Ld SOIC
NOTE: When ordering, use the entire part number. The suffixes 96
and R denote tape and reel. The suffix T denotes a small-quantity
reel of 250.
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
Q
12
Q
6
Q
5
Q7
Q
4
Q
3
GND
Q
2
V
CC
Q
10
Q
8
Q
9
MR
CP
Q
1
‘
Q
11
February 1998 - Revised October 2003
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
2003, Texas Instruments Incorporated
CD54HC4040, CD74HC4040,
CD54HCT4040, CD74HCT4040
High-Speed CMOS Logic
12-Stage Binary Counter
[ /Title
(CD74H
C4040,
CD74HC
T4040)
/Subject
(High
Speed
CMOS
Logic
12-Stage
Binary
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