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參數(shù)資料
| 型號(hào)： | CD54HC32W |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | High Speed CMOS Logic Quad 2-Input OR Gate |
| 中文描述： | 高速CMOS邏輯四路2輸入或門 |
| 文件頁數(shù)： | 1/6頁 |
| 文件大?。?/td> | 45K |
| 代理商： | CD54HC32W |
1
Data sheet acquired from Harris Semiconductor
SCHS274
Features
Typical Propagation Delay: 7ns at V
CC
= 5V,
C
L
= 15pF, T
A
= 25
o
C
Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
Wide Operating Temperature Range . . . -55
o
C to 125
o
C
Balanced Propagation Delay and Transition Times
Significant Power Reduction Compared to LSTTL
Logic ICs
HC Types
- 2V to 6V Operation
- High Noise Immunity: N
IL
= 30%, N
IH
= 30% of V
CC
at V
CC
= 5V
HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V
IL
= 0.8V (Max), V
IH
= 2V (Min)
- CMOS Input Compatibility, I
l
≤
1
μ
A at V
OL
, V
OH
Related Literature
- CD54HC32F3A and CD54HCT32F3A Military
Data Sheet, Document Number 3765
Description
The Harris CD74HC32, CD74HCT32 contain four 2-input OR
gates in one package. Logic gates utilize silicon gate CMOS
technology to achieve operating speeds similar to LSTTL
gates with the low power consumption of standard CMOS
integrated circuits. All devices have the ability to drive 10
LSTTL loads. The 74HCT logic family is functionally pin
compatible with the standard 74LS logic family.
Pinout
CD54HCT32, CD74HC32, CD74HCT32
(PDIP, CERDIP, SOIC)
TOP VIEW
Ordering Information
PART NUMBER
TEMP.RANGE
(
o
C)
PACKAGE
PKG.
NO.
CD74HC32E
-55 to 125
14 Ld PDIP
E14.3
CD74HCT32E
-55 to 125
14 Ld PDIP
E14.3
CD74HC32M
-55 to 125
14 Ld SOIC
M14.15
CD74HCT32M
-55 to 125
14 Ld SOIC
M14.15
CD54HCT32F
-55 to 125
14 Ld CERDIP
F14.3
CD54HC32W
-55 to 125
Wafer
NOTES:
1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.
2. Die for this part number is available which meets all electrical
specifications. Please contact your local sales office or Harris
customer service for ordering information.
1A
1B
1Y
2A
2B
2Y
GND
V
CC
4B
4A
4Y
3B
3A
3Y
1
2
3
4
5
6
7
14
13
12
11
10
9
8
September 1997
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
Harris Corporation 1997
File Number
1643.2
CD54HCT32, CD74HC32,
CD74HCT32
High Speed CMOS Logic
Quad 2-Input OR Gate
[ /Title
(CD54
HCT32
,
CD74
HC32,
CD74
HCT32
)
/Sub-
ject
(High
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