參數(shù)資料
型號(hào): CD4053BPWR
廠商: Texas Instruments, Inc.
英文描述: CMOS Analog Multiplexers/Demultiplexers with Logic Level Conversion
中文描述: CMOS模擬多路復(fù)用器/有邏輯電平轉(zhuǎn)換復(fù)用器
文件頁(yè)數(shù): 17/20頁(yè)
文件大?。?/td> 430K
代理商: CD4053BPWR
6
CONTROL (ADDRESS OR INHIBIT), VC
Input Low Voltage, VIL,
Max
VIL = VDD
through
1k
;
VIH = VDD
through
1k
VEE = VSS,
RL = 1k to VSS,
IIS < 2A on All
OFF Channels
5
1.5
-
1.5
V
10
3333
-
3
V
15
4444
-
4
V
Input High Voltage, VIH,
Min
5
3.5
-
V
10
7777
7
-
V
15
11
-
V
Input Current, IIN (Max)
VIN = 0, 18
18
±0.1
±1
±1-
±10-5
±0.1
A
Propagation Delay Time:
Address-to-Signal
OUT (Channels ON or
OFF) See Figures 10,
11, 14
tr, tf = 20ns,
CL = 50pF,
RL = 10k
0
5
----
-
450
720
ns
0
10
----
-
160
320
ns
0
15
----
-
120
240
ns
-5
0
5
----
-
225
450
ns
Propagation Delay Time:
Inhibit-to-Signal OUT
(Channel Turning ON)
See Figure 11
tr, tf = 20ns,
CL = 50pF,
RL = 1k
0
5
----
-
400
720
ns
0
10
----
-
160
320
ns
0
15
----
-
120
240
ns
-10
0
5
----
-
200
400
ns
Propagation Delay Time:
Inhibit-to-Signal OUT
(Channel Turning
OFF) See Figure 15
tr, tf = 20ns,
CL = 50pF,
RL = 10k
0
5
----
-
200
450
ns
0
10
----
-
90
210
ns
0
15
----
-
70
160
ns
-10
0
5
----
-
130
300
ns
Input Capacitance, CIN
(Any Address or Inhibit
Input)
----
-
5
7.5
pF
NOTE:
2. Determined by minimum feasible leakage measurement for automatic testing.
Electrical Specications
PARAMETER
TEST CONDITIONS
LIMITS
UNITS
VIS (V)
VDD (V)
RL (k)
TYP
Cutoff (-3dB) Frequency Chan-
nel ON (Sine Wave Input)
5 (Note 3)
10
1
VOS at Common OUT/IN
CD4053
30
MHz
VEE = VSS,
CD4052
25
MHz
CD4051
20
MHz
VOS at Any Channel
60
MHz
Electrical Specications
Common Conditions Here: If Whole Table is For the Full Temp. Range, VSUPPLY = ±5V, AV = +1,
RL = 100, Unless Otherwise Specied (Continued) (Note 3)
PARAMETER
CONDITIONS
LIMITS AT INDICATED TEMPERATURES (oC)
UNITS
VIS (V)
VEE (V) VSS (V) VDD (V)
-55
-40
85
125
25
MIN
TYP
MAX
20Log
V
OS
V
IS
------------
3dB
=
CD4051B, CD4052B, CD4053B
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