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參數(shù)資料
| 型號(hào)： | CD4046 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Dual Channel, 2/0, 1Mbps Digital Isolator 8-SOIC -40 to 125 |
| 中文描述： | 的CMOS微功耗鎖相環(huán) |
| 文件頁(yè)數(shù)： | 3/14頁(yè) |
| 文件大小： | 310K |
| 代理商： | CD4046 |
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Design Information
This information is a guide for approximating the value of
external components for the CD4046B in a phase-locked-
loop system The selected external components must be
within the following ranges R1 R2 t 10 kX RS t 10 kX
C1 t 50 pF
In addition to the given design information refer to
Figure 5
for R1 R2 and C1 component selections
Using Phase Comparator I
Using Phase Comparator II
Characteristics
VCO Without Offset
VCO With Offset
VCO Without Offset
VCO With Offset
R2 e %
VCO Frequency
For No Signal Input
VCO in PLL system will adjust
VCO in PLL system will adjust to
to center frequency fo
lowest operating frequency fmin
Frequency Lock
2 fL e full VCO frequency range
Range 2 fL
2fL e fmax b fmin
Frequency Capture
Range 2 fC
2fC
1
q
02
q fL
u1
Loop Filter
fC e fL
Component
Selection
For 2 fC see Ref
Phase Angle Between
90 at center frequency (fo) approximating
Always 0 in lock
Single and Comparator
0 and 180 at ends of lock range (2 fL)
Locks on Harmonics
Yes
No
of Center Frequency
Signal Input Noise
High
Low
Rejection
VCO Component
Given fo
Given fo and fL
Given fmax
Given fmin and fmax
Selection
Use fo with
Calculate fmin
Calculate fo from
Use fmin with
Figure 5a to
from the equation
the equation
Figure 5b to
determine R1
determine R2 and C1
fmin e fo b fL
and C1
fo e
fmax
2
Use fmin with Figure 5b
Calculate
fmax
fmin
to determine R2 and C1
Use fo with Figure 5a to
determine R1 and C1
Use
fmax
fmin
with
Figure 5c
Calculate
fmax
fmin
to determine ratio
from the equation
R2R1 to obtain R1
fmax
fmin
e
fo a fL
fo b fL
Use
fmax
fmin
with
Figure 5c
to determine ratio R2
R1 to obtain R1
TLF5968 – 7
TLF5968 – 9
TLF5968 – 10
TLF5968 – 8
TLF5968 – 11
TLF5968 – 12
References
GS Moschytz ‘‘Miniaturized RC Filters Using Phase-Locked Loop’’ BSTJ May 1965
Floyd Gardner ‘‘Phaselock Techniques’’ John Wiley
Sons 1966
11
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CD4060BD | CMOS 14-STAGE RIPPLE-CARRY BINARY COUNTER/DIVIDER AND OSCLLLATOR |
| CD4060BH | CMOS 14-STAGE RIPPLE-CARRY BINARY COUNTER/DIVIDER AND OSCLLLATOR |
| CD4066 | Quadruple Operational Amplifier 14-SOIC -55 to 125 |
| CD4071 | CMOS OR GATES |
| CD4071BD | CMOS OR GATES |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CD4046 WAF | 制造商:Fairchild Semiconductor Corporation 功能描述: |
| CD4046AF/3 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CD4046AF3 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CD4046AK | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CD4046BCM | 功能描述:鎖相環(huán) - PLL Phase-Locked Loop RoHS:否 制造商:Silicon Labs 類(lèi)型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
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