參數(shù)資料
型號: CD4042BC
廠商: National Semiconductor Corporation
英文描述: Quad Clocked D Latch
中文描述: 四時(shí)鐘D鎖存器
文件頁數(shù): 1/6頁
文件大?。?/td> 124K
代理商: CD4042BC
TL/F/5966
C
March 1988
CD4042BM/CD4042BC Quad Clocked D Latch
General Description
The CD4042BM/CD4042BC quad clocked ‘‘D’’ latch is a
monolithic complementary MOS (CMOS) integrated circuit
constructed with P- and N-channel enhancement mode
transistors. The outputs Q and Q either latch or follow the
data input depending on the clock level which is pro-
grammed by the polarity input. For polarity
e
0; the informa-
tion present at the data input is transferred to Q and Q
during 0 clock level; and for polarity
e
1, the transfer occurs
during the 1 clock level. When a clock transition occurs
(positive for polarity
e
0 and negative for polarity
e
1), the
information present at the input during the clock transition is
retained at the outputs until an opposite clock transition oc-
curs.
Features
Y
Wide supply voltage range
3.0V to 15V
0.45 V
DD
(typ.)
Y
High noise immunity
Y
Low power TTL
compatibility
Fan out of 2 driving 74L
or 1 driving 74LS
Y
Clock polarity control
Y
Fully buffered data inputs
Y
Q and Q outputs
Connection Diagram
Dual-In-Line Package
TL/F/5966–1
Top View
Truth Table
Clock
Polarity
Q
0
0
0
1
1
D
L
1
K
Latch
D
Latch
Order Number CD4042B
Logic Diagrams
TL/F/5966–2
TL/F/5966–3
TL/F/5966–4
C
1995 National Semiconductor Corporation
RRD-B30M105/Printed in U. S. A.
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