參數(shù)資料
型號(hào): CD4034BC
廠商: National Semiconductor Corporation
英文描述: Replaced by ISO124 :
中文描述: 8級(jí)三態(tài)雙向并行/串行輸入/輸出總線注冊(cè)
文件頁(yè)數(shù): 1/12頁(yè)
文件大小: 198K
代理商: CD4034BC
TL/F/5963
C
P
February 1988
CD4034BM/CD4034BC 8-Stage TRI-STATE
é
Bidirectional
Parallel/Serial Input/Output Bus Register
General Description
The CD4034BM/CD4034BC is an 8-bit CMOS static shift
register with two parallel bidirectional data ports (A and B)
which, when combined with serial shifting operations, can
be used to (1) bidirectionally transfer parallel data between
two buses, (2) convert serial data to parallel form and direct
them to either of two buses, (3) store (recirculate) parallel
data, or (4) accept parallel data from either of two buses
and convert them to serial form. These operations are con-
trolled by five control inputs:
A ENABLE (AE):
‘‘A’’ data port is enabled only when AE
is at logical ‘‘1’’. This allows the use of a common bus
for multiple packages.
A-BUS-TO-B-BUS/B-BUS-TO-A-BUS (A/B):
This input
controls the direction of data flow. When at logical ‘’1’’,
data flows from port A to B (A is input, B is output).
When at logical ‘‘0’’, the data flow direction is reversed.
ASYNCHRONOUS/SYNCHRONOUS (A/S):
When A/S
is at logical ‘‘0’’, data transfer occurs at positive tran-
sition of the CLOCK. When A/S is at logical ‘‘1’’, data
transfer is independent of the CLOCK for parallel opera-
tion. In serial mode, A/S input is internally disabled such
that operation is always synchronous. (Asynchronous
serial operation is not possible.)
PARALLEL/SERIAL (P/S):
A logical ‘‘1’’ P/S input al-
lows data transfer into the registers via A or B port (syn-
chronous if A/S
e
logical ‘‘0’’, asynchronous if A/S
e
logical ‘‘1’’). A logical ‘‘0’’ P/S allows serial data to
transfer into the register synchronously with the positive
transition of the CLOCK, independent of the A/S input.
CLOCK:
Single phase, enabled only in synchronous
mode. (Either P/S
e
logical ‘‘1’’ and A/S
e
logical ‘‘0’’
or P/S
e
logical ‘‘0’’.
All register stages are D-type master-slave flip-flops with
separate master and slave clock inputs generated internally
to allow synchronous or asynchronous data transfer from
master to slave.
All inputs are protected against damage due to static dis-
charge by diode clamps to V
DD
and V
SS
.
Features
Y
Wide supply voltage range
3.0V to 18V
0.45 V
DD
(typ.)
Y
High noise immunity
Y
Low power TTL
compatibility
Fan out of 2 driving 74L
or 1 driving 74LS
Y
RCA CD4034B second source
Applications
Y
Parallel Input/Parallel Output
Parallel Input/Serial Output
Serial Input/Parallel Output
Serial Input/Serial Output register
Y
Shift right/shift left register
Y
Shift right/shift left with parallel loading
Y
Address register
Y
Buffer register
Y
Bus system register with enable parallel lines at bus
side
Y
Double bus register system
Y
Up-down Johnson or ring counter
Y
Pseudo-random code generators
Y
Sample and hold register (storage, counting, display)
Y
Frequency and phase comparator
Connection Diagram
Dual-In-Line Package
TL/F/5963–1
Top View
Order Number CD4034B
TRI-STATE
é
is a registered trademark of National Semiconductor Corporation.
C
1995 National Semiconductor Corporation
RRD-B30M105/Printed in U. S. A.
相關(guān)PDF資料
PDF描述
CD4034BM
CD4034BMS CMOS 8-Stage Static Bidirectional Parallel/Serial Input/Output Bus Register(CMOS 8級(jí) 靜態(tài)雙向串/并輸入/輸出總線寄存器)
CD4035BMS CMOS 4 -Stage Parallel In/Parallel Out Shift Register(CMOS 4級(jí)并入并出移位寄存器)
CD4035 Replaced by ISO124 : Low Cost, High Voltage, Wide Bandwidth Standard Hermetic DIP Signal Isolation Buffer Amplifiers 16-CDIP SB
CD4035 4-Bit Parallel-In/Parallel-Out Shift Register
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