參數(shù)資料
型號(hào): CD4031BC
廠商: National Semiconductor Corporation
英文描述: 64-Stage Static Shift Register
中文描述: 64級(jí)靜態(tài)移位寄存器
文件頁數(shù): 1/6頁
文件大?。?/td> 145K
代理商: CD4031BC
TL/F/5962
C
February 1988
CD4031BM/CD4031BC
64-Stage Static Shift Register
General Description
The CD4031BM/CD4031BC is an integrated, complemen-
tary MOS (CMOS), 64-stage, fully static shift register. Two
data inputs, DATA IN and RECIRCULATE IN, and a MODE
CONTROL input are provided. Data at the DATA input
(when MODE CONTROL is low) or data at the RECIRCU-
LATE input (when MODE CONTROL is high), which meets
the setup and hold time requirements, is entered into the
first stage of the register and is shifted one stage at each
positive transition of the CLOCK.
Data output is available in both true and complement forms
from the 64th stage. Both the DATA OUT (Q) AND DATA
OUT (Q) outputs are fully buffered.
The CLOCK input of the CD4031BM/CD4031BC is fully
buffered, and present only a standard input load capaci-
tance. However, a DELAYED CLOCK OUTPUT (CL
D
) has
been provided to allow reduced clock drive fan-out and tran-
sition time requirements when cascading packages.
Features
Y
Wide supply voltage range
3.0V to 15V
0.45 V
DD
(typ.)
Y
High noise immunity
Y
Low power TTL
compatibility
fan out of 2 driving 74L
or 1 driving 74LS
DC to 8 MHz
V
DD
e
10V (typ.)
Y
Fully static operation
Y
Fully buffered clock input
5 pF (typ.)
input capacitance
Y
Single phase clocking requirements
Y
Delayed clock output for reduced clock drive require-
ments
Y
Fully buffered outputs
Y
High current sinking capability
1.6 mA
Y
Q output
@
V
DD
e
5V and 25
§
C
Logic and Connection Diagrams
TL/F/5962–1
Dual-In-Line Package
TL/F/5962–2
Top View
Order Number CD4031B
C
1995 National Semiconductor Corporation
RRD-B30M105/Printed in U. S. A.
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