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參數(shù)資料
| 型號(hào)： | CD4027BCMX |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 鎖存器 |
| 中文描述： | 4000/14000/40000 SERIES, DUAL POSITIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16 |
| 封裝： | 0.150 INCH, MS-012, SOIC-16 |
| 文件頁(yè)數(shù)： | 1/6頁(yè) |
| 文件大小： | 65K |
| 代理商： | CD4027BCMX |
2002 Fairchild Semiconductor Corporation
DS005958
www.fairchildsemi.com
October 1987
Revised March 2002
CD402
7BC
Dual
J-
K
Mast
er/
S
lave
Fl
ip-
F
lop
wit
h
Set
a
nd
Reset
CD4027BC
Dual J-K Master/Slave Flip-Flop with Set and Reset
General Description
The CD4027BC dual J-K flip-flops are monolithic comple-
mentary MOS (CMOS) integrated circuits constructed with
N- and P-channel enhancement mode transistors. Each
flip-flop has independent J, K, set, reset, and clock inputs
and buffered Q and Q outputs. These flip-flops are edge
sensitive to the clock input and change state on the posi-
tive-going transition of the clock pulses. Set or reset is
independent of the clock and is accomplished by a high
level on the respective input.
All inputs are protected against damage due to static dis-
charge by diode clamps to VDD and VSS.
Features
s Wide supply voltage range:
3.0V to 15V
s High noise immunity: 0.45 VDD (typ.)
s Low power TTL compatibility: Fan out of 2 driving 74L
or 1 driving 74LS
s Low power: 50 nW (typ.)
s Medium speed operation: 12 MHz (typ.) with 10V
supply
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Top View
Truth Table
I
= HIGH Level
O
= LOW Level
X
= Don't Care
= LOW-to-HIGH
= HIGH-to-LOW
Note 1: tn1 refers to the time interval prior to the positive clock pulse
transition
Note 2: tn refers to the time intervals after the positive clock pulse
transition
Note 3: Level Change
Order Number
Package Number
Package Description
CD4027BCM
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
CD4027BCN
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Inputs tn1
(Note 1)
Outputs tn
(Note 2)
CL
(Note 3)
JK
S
R
Q
I
X
OOO
I
O
X
OOO
I
O
O
X
OOO
O
I
XI
O
I
O
I
X
O
X
(No Change)
XX
X
I
O
X
I
O
XX
X
O
I
X
O
I
XX
X
I
X
I
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CD4027BCM | |
| CD4027BCN | |
| CD4040BCMX | |
| CD4040BCSJX | |
| CD4044BCMX | |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CD4027BCN | 功能描述:觸發(fā)器 Dual J-K Flip-Flop RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時(shí)間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| CD4027BD | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CD4027BD/3 | 制造商:RCA 功能描述:Flip Flop, Dual, J/K Type, 16 Pin, Ceramic, DIP |
| CD4027BD3 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CD4027BE | 功能描述:觸發(fā)器 Dual Master/Slave RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時(shí)間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
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