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參數(shù)資料
| 型號(hào)： | CD40160BMJ |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | Decade Counter with Asynchronous Clear |
| 中文描述： | 4000/14000/40000 SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP DECADE COUNTER, CDIP16 |
| 封裝： | CERAMIC, DIP-16 |
| 文件頁數(shù)： | 1/8頁 |
| 文件大?。?/td> | 150K |
| 代理商： | CD40160BMJ |
TL/F/5986
C
C
March 1988
CD40160BM/CD40160BC
Decade Counter with Asynchronous Clear
CD40161BM/CD40161BC
Binary Counter with Asynchronous Clear
CD40162BM/CD40162BC
Decade Counter with Synchronous Clear
CD40163BM/CD40163BC
Binary Counter with Synchronous Clear
General Description
These (synchronous presettable up) counters are monolith-
ic complementary MOS (CMOS) integrated circuits con-
structed with N- and P-channel enhancement mode transis-
tors. They feature an internal carry look-ahead for fast
counting schemes and for cascading packages without ad-
ditional gating.
A low level at the load input disables counting and causes
the outputs to agree with the data input after the next posi-
tive clock edge. The clear function for the CD40162B and
CD40163B is synchronous and a low level at the clear input
sets all four outputs low after the next positive clock edge.
The clear function for the CD40160B and CD40161B is
asynchronous and a low level at the clear input sets all four
outputs low, regardless of the state of the clock.
Counting is enabled when both count enable inputs are
high. Input T is fed forward to also enable the carry out. The
carry output is a positive pulse with a duration approximately
equal to the positive portion of Q
A
and can be used to en-
able successive cascaded stages. Logic transitions at the
enable P or T inputs can occur when the clock is high or
low.
Features
Y
Wide supply voltage range
3.0V to 15V
0.45 V
DD
(typ.)
Y
High noise immunity
Y
Low power TTL
compatibility
fan out of 2 driving 74L
or 1 driving 74LS
Y
Internal look-ahead for fast counting schemes
Y
Carry output for N-bit cascading
Y
Load control line
Y
Synchronously programmable
to
MC14163B
to
MM74C163
Y
Equivalent
MC14160B,
MC14161B,
MC14162B,
Y
Equivalent
MM74C160,
MM74C161,
MM74C162,
Connection Diagram
Dual-In-Line Package
TL/F/5986–1
Top View
Order Number CD40160B, CD40161B,
CD40162B or CD40163B
C
1995 National Semiconductor Corporation
RRD-B30M105/Printed in U. S. A.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CD40160BMN | Single Buffer/Driver With Open-Drain Output 5-SOT-23 -40 to 85 |
| CD40161B | Single Buffer/Driver With Open-Drain Output 5-SC70 -40 to 85 |
| CD40161BC | Single Buffer/Driver With Open-Drain Output 5-SC70 -40 to 85 |
| CD40161BCJ | Single Buffer/Driver With Open-Drain Output 5-SC70 -40 to 85 |
| CD4016BC | Single 2-Input Positive-AND Gate 5-SOT -40 to 85 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CD40160BMJ/883 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Synchronous Up Counter |
| CD40160BMN | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Decade Counter with Asynchronous Clear |
| CD40160BMS | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS Synchronous Programmable 4-Bit Counters |
| CD40160BMW | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Synchronous Up Counter |
| CD40160BMW/883 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Synchronous Up Counter |
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