參數(shù)資料
型號(hào)： CD-700-LAC-GBB-XX.XXX
廠商： Electronic Theatre Controls, Inc.
英文描述： Complete VCXO Based Phase Lock Loop
中文描述： 基于完整的石英振蕩器鎖相環(huán)
文件頁(yè)數(shù)： 13/14頁(yè)
文件大?。?/td> 147K
代理商： CD-700-LAC-GBB-XX.XXX
CD-700, VCXO Based PLL
Vectron International, 267 Lowell Rd, Hudson NH 03051-4916
Tel:1-88-VECTRON-1 Website: www.vectron.com
Page 13 of 14
Rev : 06Jul05
1
9
5
6
8
7
13
14
15
16
CLAFGAB
FREQUENCY
VI YWW
2 3 4
10
11
12
Figure 14. Outline Diagram
Table 5. Pin Function
Pin
Symbol
1
OPOUT
2
OPN
3
PHO
4
LOSIN
Function
Op-Amp Output
Op-Amp Negative Input
Phase detector Output
INPUT (Used with LOS)
Logic 0, VCXO control voltage is enabled.
Logic 1, VCXO control voltage (pin 16) is disabled and OUT1 and OUT2 are within +/-75 ppm of
center frequency
Has Internal pull-down resistor
Phase detector Input signal (TTL switching thresholds)
Phase detector Clock signal (TTL switching thresholds)
Cover and Electrical Ground
OUTPUT (Used with LOSIN)
Logic 1 if there are no transitions detected at DATAIN after 256 clock cycles at CLKIN. As soon
as a transition occurs at DATAIN, LOS is set to a logic low.
Logic 0 = Input frequency detected
Recovered Clock
Recovered Data
Divided-down VCXO Output, or Disabled
INPUT
Logic 0, OUT1, OUT2, RCLK, RDATA are set to a high impedance state.
Logic 1, OUT1, OUT2, RCLK, RDATA are active.
Has Internal pull-up resistor
VCXO Output
Power Supply Voltage (3.3 V
±
10% or 5.0 V
±
10%)
Op-Amp Positive Input
VCXO Control Voltage
5
6
7
8
DATAIN
CLKIN
GND
LOS
9
10
11
12
RCLK
RDATA
OUT2
HIZ
13
14
15
16
OUT1
V
DD
OPP
V
C
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