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參數(shù)資料
| 型號(hào)： | CCD181 |
| 廠商： | TT electronics Semelab Limited |
| 英文描述： | Variable-Element High-Speed Linear Image Sensor |
| 中文描述： | 可變?cè)馗咚倬€性圖像傳感器 |
| 文件頁(yè)數(shù)： | 4/11頁(yè) |
| 文件大小： | 481K |
| 代理商： | CCD181 |
Fairchild Imaging, Inc., 1801 McCarthy Blvd., Milpitas, CA 95035 (800)325-6975 (408) 433-2500
2
CCD181
GENERAL DESCRIPTION
The CCD181 is a 2592-element line image sensor designed for
industrial measurement, telecine, and document scanning
applications which require high resolution, high sensitivity and high
data rate. Incorporation of on-chip anti-blooming and integration
controls allow the CCD181 to be extremely useful in an industrial
measurement and control environment or in environments where
lighting conditions are difficult to control.
The CCD181 is equipped with special gates which allow the user
to select 4 effective array lengths:
2592 elements: 300-lines/inch across 8.5 inch wide document
2048 elements: 240-lines/inch across 8.5 inch wide document
1728 elements: 200-lines/inch across 8.5 inch wide document
1024 elements: 120-lines/inch across 8.5 inch wide document
The CCD181 is a third generation device having an overall improved
performance compared with first and second generation devices,
including enhanced blue response and excellent low light level per-
formance, and high-speed operation up to 20 MHz.
The photoelement size is 10
m (0.39 mils) x 10m (0.39 mils) on
10
m (0.39 mils) centers. The device is manufactured using Fairchild
Imaging’s advanced charge-coupled device n-channel isoplanar
buried-channel technology.
FUNCTIONAL DESCRIPTION
The CCD191 consists of the following functional elements illustrated
in the Block Diagram and Circuit Diagram (see Fig. 1A).
Photosites — A row of 2592 image sensor elements separated by
a diffused channel stop and covered by a silicon dioxide surface
passivation layer. Image photons pass through the transparent sili-
con creating hole-electron pairs. The photon generated electrons
are accumulated in the photosites. The amount of charge accumu-
lated in each photosite is a linear function of the incident illumination
intensity and the integration period. The output signal will vary in an
analog manner from a thermally generated background level at zero
illumination to a maximum at saturation under bright illumination.
Two Transfer Gate — Gate structures adjacent to the row of im-
age sensor elements. The charge packets accumulated in the
photosites are transferred in parallel via the transfer gates (
φX) to the
transport shift registers whenever the transfer gate voltages go high.
Alternate charge packets are transferred to the A and B transport
registers.
Two Analog Shift Registers — The transport shift registers are
used to move the light generated charge packets delivered by the
transfer gates. (
φ1A, φ1B, φ2A, φ2B) serially to the charge detector/am-
plifier. The complementary phase relationship of the last elements of
the two transport registers provides for alternate delivery of charge
packets at the output amplifiers.
A Gated Charge Detector/Amplifier — Charge packets are
transported to a precharge capacitor whose potential changes lin-
early in response to the quantity of the signal charge delivered. This
potential is applied to the input gate of the two-stage NMOS amplifi-
ers producing a signal at the output “VOUT” pin. Before each charge
packet is sensed, a reset clock (
φRA, φRB) recharges the input node
capacitor to a fixed voltage (VRDA, VRDB)
Integration and Anti-Blooming Controls — In many applica-
tions the dynamic range in parts of the image is larger than the dy-
namic range of the CCD, which may cause more electrons to be
generated in the photosite area than can be stored in the CCD shift
register. This is particularly common in industrial inspection and sat-
ellite applications. The excess electrons generated by bright illumi-
nation tend to “bloom” or “spill over” to neighboring pixels along the
shift register, thus “smearing” the information. This smearing can be
eliminated using two methods:
Anti-Blooming Operation:
A DC voltage applied to the integration control gate (approximately 5
to 7 volts) will cause excess charge generated in the photosites to be
diverted to the anti-blooming sink (VSINK) instead of to the shift regis-
ters. This acts as a “clipping circuit” for the CCD output. (see Fig. 2)
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