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| 型號： | CCD153CM |
| 英文描述： | Optoelectronic |
| 中文描述： | 光電 |
| 文件頁數(shù)： | 2/12頁 |
| 文件大?。?/td> | 614K |
| 代理商： | CCD153CM |
Fairchild Imaging, Inc.,
1801 McCarthy Blvd., Milpitas, CA 95035 (800)325-6975 (408) 433-2500
2
CCD133A
FUNCTIONAL DESCRIPTION
The CCD133A consists of the following functional elements illus-
trated in the Block Diagram and Circuit Diagram (Fig1.).
Photosites:
A row of 1024 image sensor elements separated by
a diffused channel stop and covered by a silicon dioxide surface
passivation layer. Image photons pass through the transparent sili-
con creating hole-electron pairs. The photon generated electrons
are accumulated in the photosites. The amount of charge accumu-
lated in each photosite is a linear function of the incident illumination
intensity and the integration period. The output signal will vary in an
analog manner from a thermally generated background level at zero
illumination to a maximum at saturation under bright illumination.
Photogate:
The photogate structure, located at the edge of the
photosites, provides a bias voltage for the photosites.
Transfer Gate:
The transfer gate structure separates the outer
edge of the photogates from the analog shift registers. Charge-
packets generated and accumulated in the photosites are transferred
into the transport analog shift registers whenever the transfer gate
voltage goes “High”. All odd-numbered charge packets are trans-
ferred into the “A” transport analog shift register: all even-numbered
charge packets are transferred into the “B” transport analog shift
register. The transfer gate also controls the input of charge from V
EI
into the white reference cells (described below). The time interval
between successive transfer pulses determines the integration time.
Analog Shift Registers:
Four 529-element analog shift regis-
ters transport charge towards the output end of the chip. the two
inner registers, the transport registers, move the image generated
charge packets serially to the two gated charge detectors and am-
plifiers. The two outer shift registers, the peripheral registers, accu-
mulate charge generated at the chip periphery (by photons passing
through unavoidable gaps in the light shield layer, etc.) and trans-
port it to charge sinks. The primary shift register clock is
φ
T
. The
complementary phase relationship of the secondary shift register
clocks
φ
T
and
φ
T
, generated on-chip, provide alternate delivery of
charge packets from “A” and “B” shift registers to their amplifiers so
that the original serial sequential string of video information may be
easily demutiplexed off-chip.
Gated Charge Detectors & Reset Gates:
Each transport ana-
log shift register delivers charge packets to a precharged diode. The
change in diode potential is linearly proportional to the amount of
charge delivered in the charge packet. This potential is applied to the
input gate of a MOS transistor amplifier (see below), which linearly
amplifies the input potential. The diode is reset to the reset drain
bias voltage (V
RD
) by the reset gate structure. Reset occurs when
both the internal reset clocks (
φ
T
on the “A: side,
φ
T
on the “B” side)
are “High.” Each side is reset just before the next charge packet is
delivered from its respective transport analog shift register.
Output Amplifiers and Sample-and Hold Gates:
Each sides’
gated charge integrator drives the input of a two-stage linear MOS-
transistor amplifier. A schematic diagram of this circuit is shown in
Figure 9 below. The two stages of each amplifier are separated by
sample-and-hold gates. The output of the first stage is connected to
the input of the second stage whenever the sample-and-hold gates is
“High”. The output of the second stage is connected to the VIDEO
OUT
pin. The sample-and-hold gates are switching MOS transistors: clock-
ing these gates results in a sampled-and-held output, thus eliminat-
ing the reset clock feedthrough. When on-chip sample-and-hold is
used, pin 2 is to be tied to pin 3 and pin 21 is to be tied to pin 22. Off-
chip sample-and hold pulses can be supplied through pins 2 and 22.
The sample-and-hold operation can be disabled by tying pins 2 and
22 to V
DD
. Whenever on-chip sample-and hold is not used, pins 3
and 21 should be left unconnected.
Clock Driver Circuits:
Two MOSFET clock-driver circuits on-
chip allow sample-and-held operation of the CCD133A with only two
externally-supplied clocks: the square-wave primary shift register
transport clock
φ
T
, which determines the output data rate, and the
transfer clock
φ
X
, which determines the integration time.
Dark Reference Circuitry:
Four additional sensing elements at
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