參數(shù)資料
型號: CBTD3306PW
廠商: NXP Semiconductors N.V.
元件分類: 開關(guān)
英文描述: Dual bus switch with level shifting
中文描述: 雙總線電平轉(zhuǎn)換開關(guān)
封裝: CBTD3306D<SOT96-1 (SO8)|<<http://www.nxp.com/packages/SOT96-1.html<1<week 5, 2005,;CBTD3306D<SOT96-1 (SO8)|<<http://www.nxp.com/packages/SOT96-1.html<1<week 5, 2005
文件頁數(shù): 15/17頁
文件大小: 140K
代理商: CBTD3306PW
CBTD3306
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product Specification
Rev. 5 — 28 April 2011
7 of 17
NXP Semiconductors
CBTD3306
Dual bus switch with level shifting
11. Dynamic characteristics
[1]
The propagation delay is the calculated RC time constant of the typical ON resistance of the switch and the specified load capacitance,
when driven by an ideal voltage source (zero output impedance).
[2]
tpd is the same as tPLH and tPHL.
ten is the same as tPZL and tPZH.
tdis is the same as tPLZ and tPHZ.
12. Waveforms
Table 8.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 13.
Symbol
Parameter
Conditions
Tamb =
40 °C to +85 °C
Unit
Min
Typ
Max
tpd
propagation delay
nA, nB to nB, nA; see Figure 11
-
0.25
ns
VCC = 5.0 V
± 0.5 V
ten
enable time
nOE to nA or nB; see Figure 12
1.0
-
5.4
ns
VCC = 5.0 V
± 0.5 V
tdis
disable time
nOE to nA or nB; see Figure 12
1.0
-
4.9
ns
VCC = 5.0 V
± 0.5 V
Measurement points are given in Table 9.
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Fig 11. The data input (nA, nB) to output (nB, nA) propagation delay times
001aak305
tPLH
tPHL
VM
nB, nA
output
nA, nB
input
VI
GND
VOH
VOL
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