參數(shù)資料
型號: CBTD16210
廠商: NXP Semiconductors N.V.
英文描述: 20-bit level shifting bus switch with 10-bit output enables
中文描述: 帶有10位使能輸出的20位電平轉換總線開關
文件頁數(shù): 5/10頁
文件大小: 82K
代理商: CBTD16210
Philips Semiconductors
Product specification
CBTD16210
20-bit level shifting bus switch
with 10-bit output enables
2000 Oct 12
5
AC CHARACTERISTICS
GND = 0 V; t
R;
C
L
= 50 pF
SYMBOL
PARAMETER DESCRIPTION
LIMITS
–40
°
C to +85
°
C V
CC
= 5 V
±
0.5 V
Min
Mean
UNITS
Max
t
pd
t
PZH
t
PHZ
t
PZL
t
PLZ
Propagation delay
1
250
ps
Output enable time to HIGH level
1.5
5.0
7.5
ns
Output disable time from HIGH level
1.0
2.5
4.5
ns
Output enable time to LOW level
1.5
6.0
9.0
ns
Output disable time from LOW level
1.5
3.5
6.0
ns
NOTES:
1. This parameter is warranted but not production tested. The propagation delay is based on the RC time constant of the typical on-state
resistance of the switch and a load capacitance of 50 pF, when driven by an ideal voltage source (zero output impedance).
AC WAVEFORMS
V
M
= 1.5 V, V
IN
= GND to 3.0 V
INPUT
1.5V
OUTPUT
t
PLH
t
PHL
SA00028
1.5V
1.5V
1.5V
3 V
0 V
V
OH
V
OL
Waveform 1. Input (An) to Output (Yn) Propagation Delays
Output Control
(Low-level
enabling
1.5 V
t
PZH
t
PHZ
V
OH
V
OL
t
PZL
t
PLZ
3.5V
0V
V
OL
+ 0.3V
V
OH
– 0.3V
SA00029
1.5 V
1.5 V
1.5 V
0V
3V
Output
Waveform 1
S1 at 7 V
(see Note)
Note:
Waveform 1 is for an output with internal conditions such that
the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that
the output is high except when disabled by the output control.
Output
Waveform 2
S1 at Open
(see Note)
Waveform 2. 3-State Output Enable and Disable Times
TEST CIRCUIT AND WAVEFORMS
C
L
= 50 pF
500
Load Circuit
DEFINITIONS
C
L
=
Load capacitance includes jig and probe capacitance;
see AC CHARACTERISTICS for value.
TEST
S1
t
pd
open
t
PLZ
/t
PZL
7 V
t
PHZ
/t
PZH
open
SA00012
500
From Output
Under Test
S1
7 V
Open
GND
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