參數資料
型號: CBT6832EDGG
廠商: NXP SEMICONDUCTORS
元件分類: 通用總線功能
英文描述: 16-bit controlled enable rate 1-of-2 multiplexer/demultiplexer with precharged outputs and Schottky undershoot protection for live insertion
中文描述: CBT/FST/QS/5C/B SERIES, 16 1 LINE TO 2 LINE MULTIPLEXER AND DEMUX/DECODER, TRUE OUTPUT, PDSO56
封裝: 6.10 MM, PLASTIC, MO-153, SOT-364-1, TSSOP2-56
文件頁數: 5/8頁
文件大?。?/td> 67K
代理商: CBT6832EDGG
Philips Semiconductors
Product specification
CBT6832E
16-bit controlled enable rate 1-of-2 multiplexer/demultiplexer with precharged
outputs and Schottky undershoot protection for live insertion
2000 Sep 01
5
AC CHARACTERISTICS
V
CC
= 5.0 V
±
0.5 V; GND = 0 V
;
C
L
= 50 pF, R
L
= 500
SYMBOL
PARAMETER
TEST CONDITIONS
LIMITS
TYP
UNIT
MIN
MAX
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
Propagation delay
1
A to B
Bus enable time
SEL to A, B
Bus disable time
SEL to A, B
Waveform 1
0.25
ns
Waveform 2
10
5
0.5
0.5
30
25
6
7
ns
Waveform 2
ns
NOTE:
1. This parameter is warranted but not production tested. The propagation delay is based on the RC time constant of the typical on-state
resistance of the switch and a load capacitance of 50 pF, when driven by an ideal voltage source (zero output impedance).
AC WAVEFORMS
V
M
= 1.5 V, V
IN
= GND to 3.0 V
INPUT
1.5V
OUTPUT
t
PLH
t
PHL
SA00028
1.5V
1.5V
1.5V
3 V
0 V
V
OH
V
OL
Waveform 1. Input (An) to Output (Bn) Propagation Delays
Output Control
(Low-level
enabling
1.2 V
t
PZH
t
PHZ
V
OH
V
OL
t
PZL
t
PLZ
2.3V
0V
V
OL
+ 0.3V
V
OH
– 0.3V
1.2 V
1.5 V
1.5 V
0V
3V
Output
Waveform 1
S1 at 7 V
(see Note)
Note:
Waveform 1 is for an output with internal conditions such that
the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that
the output is high except when disabled by the output control.
Output
Waveform 2
S1 at Open
(see Note)
SA00530
Waveform 2. 3-State Output Enable and Disable Times
TEST CIRCUIT AND WAVEFORMS
C
L
= 50 pF
500
Load Circuit
DEFINITIONS
C
L
=
Load capacitance includes jig and probe capacitance;
see AC CHARACTERISTICS for value.
TEST
S1
t
pd
open
t
PLZ
/t
PZL
7 V
t
PHZ
/t
PZH
open
SA00012
500
From Output
Under Test
S1
7 V
Open
GND
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