參數(shù)資料
型號: CB55000
英文描述: HCMOS7 STANDARD CELLS
中文描述: HCMOS7標(biāo)準(zhǔn)單元
文件頁數(shù): 1/15頁
文件大?。?/td> 2533K
代理商: CB55000
1/15
CB55000 Series
February 2002
FEATURE
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0.25 micron drawn (0.20 micron effective
channel length process), six layers of metal
connected by fully stackable vias and contacts,
Shallow Trench Isolation, low resistance,
salicided active areas and gates. Deep UV
lithography.
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2.5 V optimized transistor with 3.3 V I/O and
supply interface capability.
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Average gate density: 30 K/mm2, plus low
power consumption of 70 nanoWatt/Gate/MHz/
Stdload.
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Two input NAND delay of 90 pS (typical) with
fanout=2.
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Library available in commercial, industrial and
military temperature range with supply ranging
from 2.70 V down to 1.8 V for the core
according to EIA/JESD 8-5 specification.
Additional low voltage range down to 1.5 V for
very low voltage/low power applications
supported
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Broad I/O functionality including:
– Low Voltage CMOS.
– Low Voltage TTL, PECL, HSTL, SSTL,
LVDS, PCI.
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AGP 2X and 4X, USB to support 2.5 V and 3.3
V I/O interface according to EIA/JESD 8A
specification.
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Drive capability up to 8 mA per buffer with slew
rate control, current spike suppression
impedance matching, and process
compensation capability to reduce delay
variation.
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Designs easily portable from previous
generations of CB45000 through cell mapping
with an average factor 2 density increase, 1.7
speed increase and 2.5 power reduction at
respective nominal voltages.
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Generators to support Single Port, Dual port
and multiple Port RAM, and ROMs with BIST
options.
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Extensive embedded function library including
ST DSP and micro-cores, third-party IPs,
Synopsys and Mentor Inventra synthetic
libraries ideally suited for complete System On
Chip fast integration .
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80
μ
m pitch linear and 50
μ
m staggered pad
libraries.
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Fully independent power and ground
configuration for core and I/Os supported.
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I/O ring capability up to 1500 pads.
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Latch-up trigger current > +/- 500 mA. ESD
protection above 4 kV in H.B.M.
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Oscillators and PLLs for wide frequency
spectrum.
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Broad range of more than 600 SSI cells.
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Design for test features including IEEE 1149.1
JTAG Boundary Scan architecture.
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Synopsys, Cadence and Mentor based design
systems with interface from multiple
workstations.
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Broad range of packaging solutions, including
BGA, LBGA, TQFP, PQFP, PLCC up to 1000
pins with enhanced power dissipation options.
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1.25 GigaHertzGigabit DLL technique.
CB55000 Super Integration
Cost Effective Product
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Architecture partitioning
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Trouble-free integration
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Application-specific
Your Product is Unique
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User specified cell integration
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Design confidentiality
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IP fully re-usable
DPRAM
ST20
ROM
DSP
HCMOS7 Standard Cells
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