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參數(shù)資料
| 型號： | CAT9554AYI-GT2 |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 12/14頁 |
| 文件大小： | 0K |
| 描述： | IC I/O EXPANDER I2C 8B 16TSSOP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 接口： | I²C，SM 總線 |
| 輸入/輸出數(shù)： | 8 |
| 中斷輸出： | 是 |
| 頻率 - 時鐘： | 400kHz |
| 電源電壓： | 2.3 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-TSSOP |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 包括： | POR |
| 產(chǎn)品目錄頁面： | 806 (CN2011-ZH PDF) |
| 其它名稱： | CAT9554AYI-GT2DKR |
CAT9554, CAT9554A
http://onsemi.com
7
Functional Description
The CAT9554 and CAT9554A general purpose input/
output (GPIO) peripherals provide up to eight I/O ports,
controlled through an I2C compatible serial interface.
The CAT9554/9554A support the I2C Bus data
transmission protocol. This I2C Bus protocol defines any
device that sends data to the bus to be a transmitter and any
device receiving data to be a receiver. The transfer is
controlled by the Master device which generates the serial
clock and all START and STOP conditions for bus access.
The CAT9554/9554A operate as a Slave device. Both the
Master device and Slave device can operate as either
transmitter or receiver, but the Master device controls which
mode is activated.
I2C Bus Protocol
The features of the I2C bus protocol are defined as follows:
1. Data transfer may be initiated only when the bus is
not busy.
2. During a data transfer, the data line must remain
stable whenever the clock line is high. Any
changes in the data line while the clock line is high
will be interpreted as a START or STOP condition
(Figure 6).
START and STOP Conditions
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of SDA
when SCL is HIGH. The CAT9554/9554A monitors the
SDA and SCL lines and will not respond until this condition
is met.
A LOW to HIGH transition of SDA when SCL is HIGH
determines the STOP condition. All operations must end
with a STOP condition.
Device Addressing
After the bus Master sends a START condition, a slave
address byte is required to enable the CAT9554/9554A for
a read or write operation. The four most significant bits of
the slave address are fixed as binary 0100 for the CAT9554
CAT9554/9554A uses the next three bits as address bits.
The address bits A2, A1 and A0 are used to select which
device is accessed from maximum eight devices on the same
bus. These bits must compare to their hardwired input pins.
The 8th bit following the 7bit slave address is the R/W bit
that specifies whether a read or write operation is to be
performed. When this bit is set to “1”, a read operation is
initiated, and when set to “0”, a write operation is selected.
Following the START condition and the slave address
byte, the CAT9554/9554A monitors the bus and responds
with an acknowledge (on the SDA line) when its address
matches the transmitted slave address. The CAT9554/
9554A then performs a read or a write operation depending
on the state of the R/W bit.
START
CONDITION
STOP
CONDITION
SDA
SCL
Figure 6. START/STOP Condition
0
1
0
A2A1A0
SLAVE ADDRESS
FIXED
PROGRAMMABLE
HARDWARE
SELECTABLE
Figure 7. CAT9554 Slave Address
R/W
0
1
A2A1A0
SLAVE ADDRESS
FIXED
PROGRAMMABLE
HARDWARE
SELECTABLE
Figure 8. CAT9554A Slave Address
R/W
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CAT9554HV4 | 制造商:Catalyst Semiconductor 功能描述: |
| CAT9554HV4I | 制造商:Rochester Electronics LLC 功能描述: 制造商:Catalyst Semiconductor 功能描述: |
| CAT9554HV4I-GT2 | 功能描述:接口-I/O擴展器 I2C/SMBUS Expander 8B,w/Int RoHS:否 制造商:NXP Semiconductors 邏輯系列: 輸入/輸出端數(shù)量: 最大工作頻率:100 kHz 工作電源電壓:1.65 V to 5.5 V 工作溫度范圍:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:HVQFN-16 封裝:Reel |
| CAT9554HV4I-T2 | 功能描述:接口 - 專用 I2C/SMBUS Expander 8B,w/Int RoHS:否 制造商:Texas Instruments 產(chǎn)品類型:1080p60 Image Sensor Receiver 工作電源電壓:1.8 V 電源電流:89 mA 最大功率耗散: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:BGA-59 |
| CAT9554HV6I | 制造商:Rochester Electronics LLC 功能描述: 制造商:Catalyst Semiconductor 功能描述: |
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