參數(shù)資料
型號(hào): CAT9534YI-GT2
廠商: ON Semiconductor
文件頁(yè)數(shù): 2/14頁(yè)
文件大小: 0K
描述: IC I/O EXPANDER I2C 8B 16TSSOP
標(biāo)準(zhǔn)包裝: 1
接口: I²C,SM 總線
輸入/輸出數(shù): 8
中斷輸出:
頻率 - 時(shí)鐘: 400kHz
電源電壓: 2.3 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 16-TSSOP
包裝: 標(biāo)準(zhǔn)包裝
包括: POR
產(chǎn)品目錄頁(yè)面: 806 (CN2011-ZH PDF)
其它名稱: CAT9534YI-GT2DKR
CAT9534
http://onsemi.com
10
Interrupt Output
CAT9534’s interrupt otuput is an active LOW opendrain
output that is activated when any port pin configured as an
input changes state. The interrupt output is reset when the
input returns to its previous state or the Input Port Register
is read.
Note that changing an I/O from an output to an input may
cause a false interrupt to occur if the state of the pin does not
match the contents of the Input Port register.
PowerOn Reset Operation
When the power supply is applied to VCC pin, an internal
poweron reset pulse holds the CAT9534 in a reset state until
VCC reaches VPOR level. At this point, the reset condition is
released and the internal state machine and the CAT9534’s
registers are initialized to their default state.
12
34
5
6
7
8
9
SCL
SDA
READ FROM
PORT
DATA INTO
PORT
S 0100 A2
A0 1
A
A1
A
DATA 4
NA P
no acknowledge
from master
acknowledge
from master
acknowledge
from slave
slave address
data from port
start condition
stop
condition
DATA 2
DATA 3
DATA 4
DATA 1
data from port
DATA 1
DATA
S 0100 A2
A0 0
A
A1
0 1 0 0 A2 A1 A0
A
DATA
A
acknowledge from master
acknowledge from slave
slave address
data from register
COMMAND BYTE
AS
1
acknowledge from slave
At this moment mastertransmitter becomes
masterreceiver and slavereceiver
becomes slavetransmitter
NA
no acknowledge
from master
data from register
P
last byte
first byte
Figure 11. Read from Register
Figure 12. Read Input Port Register
tIR
tIV
INT
tPH
R/W
tPS
R/W
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