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參數(shù)資料
| 型號(hào)： | CAT93C76ZD4I-1.8REVA |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | PROM |
| 英文描述： | 512 X 16 MICROWIRE BUS SERIAL EEPROM, DSO8 |
| 封裝： | 3 X 3 MM, LEAD AND HALOGEN FREE, TDFN-8 |
| 文件頁(yè)數(shù)： | 5/10頁(yè) |
| 文件大?。?/td> | 405K |
| 代理商： | CAT93C76ZD4I-1.8REVA |
4
CAT93C76
Doc. No. 1090, Rev. M
A.C. TEST CONDITIONS
Input Rise and Fall Times
≤ 50ns
Input Pulse Voltages
0.4V to 2.4V
4.5V
≤ VCC ≤ 5.5V
Timing Reference Voltages
0.8V, 2.0V
4.5V
≤ VCC ≤ 5.5V
Input Pulse Voltages
0.2VCC to 0.7VCC
1.8V
≤ VCC ≤ 4.5V
Timing Reference Voltages
0.5VCC
1.8V
≤ VCC ≤ 4.5V
POWER-UP TIMING (1)(2)
Symbol
Parameter
Max
Units
tPUR
Power-up to Read Operation
1
ms
tPUW
Power-up to Write Operation
1
ms
NOTE:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
DEVICE OPERATION
The CAT93C76 is a 8192-bit nonvolatile memory in-
tended for use with industry standard microprocessors.
The CAT93C76 can be organized as either registers of
16 bits or 8 bits. When organized as X16, seven 13-bit
instructions control the reading, writing and erase opera-
tions of the device. When organized as X8, seven 14-bit
instructions control the reading, writing and erase
operations of the device. The CAT93C76 operates on
a single power supply and will generate on chip, the high
voltage required during any write operation.
Instructions, addresses, and write data are clocked into
the DI pin on the rising edge of the clock (SK). The DO
pin is normally in a high impedance state except when
reading data from the device, or when checking the
ready/busy status after a write operation.
The ready/busy status can be determined after the start
of a write operation by selecting the device (CS high) and
polling the DO pin; DO low indicates that the write
operation is not completed, while DO high indicates that
the device is ready for the next instruction. If necessary,
the DO pin may be placed back into a high impedance
state during chip select by shifting a dummy “1” into the
DI pin. The DO pin will enter the high impedance state on
the falling edge of the clock (SK). Placing the DO pin into
the high impedance state is recommended in applica-
tions where the DI pin and the DO pin are to be tied
together to form a common DI/O pin.
The format for all instructions sent to the device is a
logical "1" start bit, a 2-bit (or 4-bit) opcode, 10-bit
address (an additional bit when organized X8) and for
write operations a 16-bit data field (8-bit for X8
organizations). The most significant bit of the address is
“don’t care” but it must be kept either high or low.
Read
Upon receiving a READ command and an address
(clocked into the DI pin), the DO pin of the CAT93C76 will
come out of the high impedance state and, after sending
an initial dummy zero bit, will begin shifting out the data
addressed (MSB first). The output data bits will toggle on
the rising edge of the SK clock and are stable after the
specified time delay (tPD0 or tPD1).
For the CAT93C76 after the initial data word has been
shifted out and CS remains asserted with the SK clock
continuing to toggle, the device will automatically
increment to the next address and shift out the next data
word in a sequential READ mode. As long as CS is
continuously asserted and SK continues to toggle, the
device will keep incrementing to the next address
automatically until it reaches to the end of the address
space, then loops back to address 0. In the sequential
READ mode, only the initial data word is preceeded by
a dummy zero bit. All subsequent data words will follow
without a dummy zero bit.
Write
After receiving a WRITE command, address and the
data, the CS (Chip Select) pin must be deselected for a
minimum of tCSMIN. The falling edge of CS will start the
self clocking clear and data store cycle of the memory
location specified in the instruction. The clocking of the
SK pin is not necessary after the device has entered the
self clocking mode. The ready/busy status of the
CAT93C76 can be determined by selecting the device
and polling the DO pin. Since this device features Auto-
Clear before write, it is NOT necessary to erase a
memory location before it is written into.
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| CAT93C76ZD4I-GT3 | 功能描述:電可擦除可編程只讀存儲(chǔ)器 8KB MICROWIRE Serial 電可擦除可編程只讀存儲(chǔ)器 RoHS:否 制造商:Atmel 存儲(chǔ)容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時(shí)鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 |
| CAT93C86BHU4I-GT3 | 功能描述:IC EEPROM 16KB SPI SER 8UDFN 制造商:on semiconductor 系列:- 包裝:帶卷（TR） 零件狀態(tài):有效 格式 - 存儲(chǔ)器:EEPROMs - 串行 存儲(chǔ)器類型:EEPROM 存儲(chǔ)容量:16K（2K x 8，1K x 16） 速度:4MHz 接口:Microwire 3 線串行 電壓 - 電源:1.8 V ~ 5.5 V 工作溫度:-40°C ~ 85°C（TA） 封裝/外殼:8-UFDFN 裸露焊盤(pán) 供應(yīng)商器件封裝:8-UDFN（2x3） 標(biāo)準(zhǔn)包裝:3,000 |
| CAT93C86KI | 制造商:Catalyst Semiconductor 功能描述: |
| CAT93C86L | 功能描述:電可擦除可編程只讀存儲(chǔ)器 (2048x8)(1024x16)16K RoHS:否 制造商:Atmel 存儲(chǔ)容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時(shí)鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 |
| CAT93C86L-1.8 | 功能描述:電可擦除可編程只讀存儲(chǔ)器 (2048x8)(1024x16)16K RoHS:否 制造商:Atmel 存儲(chǔ)容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時(shí)鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 |
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