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參數(shù)資料
| 型號(hào)： | CAT93C46WI-GT3 |
| 英文描述： | 1-Kb Microwire Serial EEPROM |
| 中文描述： | 1 - KB的微型導(dǎo)線串行EEPROM |
| 文件頁數(shù)： | 6/15頁 |
| 文件大?。?/td> | 136K |
| 代理商： | CAT93C46WI-GT3 |
CAT93C46
6
Doc No. 1106, Rev. F
200
7
by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Write
After receiving a WRITE command (Figure 4), address
and the data, the CS (Chip Select) pin must be deselected
for a minimum of t
CSMIN
. The falling edge of CS will start
the self clocking for auto-clear and data store cycles on
the memory location specified in the instruction. The
clocking of the SK pin is not necessary after the device
has entered the self clocking mode. The ready/busy
status of the CAT93C46 can be determined by selecting
the device and polling the DO pin. Since this device
features Auto-Clear before write, it is NOT necessary to
erase a memory location before it is written into.
Erase
Upon receiving an ERASE command and address, the
CS (Chip Select) pin must be deasserted for a minimum
of t
CSMIN
(Figure 5). The falling edge of CS will start the
self clocking clear cycle of the selected memory location.
The clocking of the SK pin is not necessary after the
device has entered the self clocking mode. The ready/
busy status of the CAT93C46 can be determined by
selecting the device and polling the DO pin. Once
cleared, the content of a cleared location returns to a
logical
“
1
”
state.
Erase All
Upon receiving an ERAL command (Figure 6), the CS
(Chip Select) pin must be deselected for a minimum of
t
CSMIN
. The falling edge of CS will start the self clocking
clear cycle of all memory locations in the device. The
clocking of the SK pin is not necessary after the device
has entered the self clocking mode. The ready/busy
status of the CAT93C46 can be determined by selecting
the device and polling the DO pin. Once cleared, the
contents of all memory bits return to a logical
“
1
”
state.
Write All
Upon receiving a WRAL command and data, the CS
(Chip Select) pin must be deselected for a minimum of
t
CSMIN
(Figure 7). The falling edge of CS will start the self
clocking data write to all memory locations in the device.
The clocking of the SK pin is not necessary after the
device has entered the self clocking mode. The ready/
busy status of the CAT93C46 can be determined by
selecting the device and polling the DO pin. It is not
necessary for all memory locations to be cleared before
the WRAL command is executed.
Figure 4. Write Instruction Timing
SK
CS
DI
DO
tCSMIN
STANDBY
HIGH-Z
HIGH-Z
1
0
1
AN
AN-1
A0
DN
D0
BUSY
READY
STATUS
VERIFY
tSV
tHZ
tEW
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CAT93C46LI-GT2 | 1-Kb Microwire Serial EEPROM |
| CAT93C46LI-GT3 | 1-Kb Microwire Serial EEPROM |
| CAT93C46LIT2 | 1-Kb Microwire Serial EEPROM |
| CAT93C46LIT3 | 1-Kb Microwire Serial EEPROM |
| CAT93C46VI-GT2 | 1-Kb Microwire Serial EEPROM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CAT93C46WIT2 | 制造商:CATALYST 制造商全稱:Catalyst Semiconductor 功能描述:1-Kb Microwire Serial EEPROM |
| CAT93C46WI-T2 | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:1 kb Microwire Serial EEPROM |
| CAT93C46WIT3 | 制造商:CATALYST 制造商全稱:Catalyst Semiconductor 功能描述:1-Kb Microwire Serial EEPROM |
| CAT93C46WI-T3 | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:1 kb Microwire Serial EEPROM |
| CAT93C46WI-TE13 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:EEPROM |
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