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參數(shù)資料
| 型號： | CAT93C46RYI-GT |
| 英文描述： | 1-Kb Microwire Serial EEPROM |
| 中文描述： | 1 - KB的微型導線串行EEPROM |
| 文件頁數(shù)： | 6/13頁 |
| 文件大?。?/td> | 492K |
| 代理商： | CAT93C46RYI-GT |
CAT93C46R
6
Doc. No. 1107, Rev. F
2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
SK
CS
DI
DO
tCS MIN
STANDBY
HIGH-Z
HIGH-Z
1
0
1
AN
AN-1
A0
DN
D0
BUSY
READY
STATUS
VERIFY
tSV
tHZ
tEW
Figure 4. Write Instruction Timing
Write
After receiving a WRITE command, address and the
data, the CS (Chip Select) pin must be deselected for a
minimum of t
CSMIN
(see
Design Note
for details). The
falling edge of CS will start the self clocking clear and
data store cycle of the memory location specified in the
after the device has entered the self clocking mode.
The ready/busy status of the CAT93C46R can be
determined by selecting the device and polling the DO
pin. Since this device features Auto-Clear before write,
it is NOT necessary to erase a memory location before
it is written into.
Erase
Upon receiving an ERASE command and address, the
CS (Chip Select) pin must be deasserted for a minimum
of t
CSMIN
after the proper number of clock pulses (see
Design Note
). The falling edge of CS will start the self
clocking clear cycle of the selected memory location.
The clocking of the SK pin is not necessary after the
device has entered the self clocking mode. The ready/
busy status of the CAT93C46R can be determined by
selecting the device and polling the DO pin. Once
cleared, the content of a cleared location returns to a
logical
“
1
”
state.
Erase All
Upon receiving an ERAL command, the CS (Chip Select)
pin must be deselected for a minimum of t
CSMIN
. The
falling edge of CS will start the self clocking clear cycle
of all memory locations in the device. The clocking of the
SK pin is not necessary after the device has entered the
self clocking mode. The ready/busy status of the
CAT93C46R can be determined by selecting the device
and polling the DO pin. Once cleared, the contents of all
memory bits return to a logical
“
1
”
state.
Write All
Upon receiving a WRAL command and data, the CS
(Chip Select) pin must be deselected for a minimum of
t
CSMIN
. The falling edge of CS will start the self clocking
data write to all memory locations in the device. The
clocking of the SK pin is not necessary after the device
has entered the self clocking mode.
(Note 1.)
The ready/
busy status of the CAT93C46R can be determined by
selecting the device and polling the DO pin. It is not
necessary for all memory locations to be cleared before
the WRAL command is executed.
Design Note
With CAT93C46R, after the last data bit has been
sampled, Chip Select (CS) must be brought Low before
the next rising edge of the clock(SK) in order to start the
slef-timed high voltage cycle. This is important because
if the CS is brought low before or after this specific frame
window, the addressed location will not be programmed
or erased.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CAT93C46RYI-GT3 | 功能描述:電可擦除可編程只讀存儲器 1K-Bit Microwire RoHS:否 制造商:Atmel 存儲容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-8 |
| CAT93C46S | 功能描述:電可擦除可編程只讀存儲器 (128x8) / (64x16) 1K RoHS:否 制造商:Atmel 存儲容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-8 |
| CAT93C46S-1.8 | 功能描述:電可擦除可編程只讀存儲器 (128x8) / (64x16) 1K RoHS:否 制造商:Atmel 存儲容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-8 |
| CAT93C46S-1.8TE13 | 制造商:CATALYST 制造商全稱:Catalyst Semiconductor 功能描述:1K/2K/2K/4K/16K-Bit Microwire Serial E2PROM |
| CAT93C46S-2.5 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microwire Serial EEPROM |
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