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參數(shù)資料
| 型號： | CAT93C46 |
| 英文描述： | 1K-Bit Microwire Serial EEPROM(1K位微導(dǎo)線串行EEPROM) |
| 中文描述： | 1K位微型導(dǎo)線串行EEPROM（每1000位微導(dǎo)線串行EEPROM的） |
| 文件頁數(shù)： | 7/9頁 |
| 文件大小： | 61K |
| 代理商： | CAT93C46 |
7
93C46/56/57/66/86
Doc. No. 25056-00 2/98 M-1
Erase
Upon receiving an ERASE command and address, the
CS (Chip Select) pin must be deasserted for a minimum
of t
CSMIN
. The falling edge of CS will start the self clocking
clear cycle of the selected memory location. The clock-
ing of the SK pin is not necessary after the device has
entered the self clocking mode. The ready/busy status of
the CAT93C46/56/57/66/86 can be determined by se-
lecting the device and polling the DO pin. Once cleared,
the content of a cleared location returns to a logical “1”
state.
Erase/Write Enable and Disable
The CAT93C46/56/57/66/86 powers up in the write
disable state. Any writing after power-up or after an
EWDS (write disable) instruction must first be preceded
by the EWEN (write enable) instruction. Once the write
instruction is enabled, it will remain enabled until power
to the device is removed, or the EWDS instruction is
sent. The EWDS instruction can be used to disable all
CAT93C46/56/57/66/86 write and clear instructions,
and will prevent any accidental writing or clearing of the
device. Data can be read normally from the device
regardless of the write enable/disable status.
Erase All
Upon receiving an ERAL command, the CS (Chip Se-
lect) pin must be deselected for a minimum of t
CSMIN
.
The falling edge of CS will start the self clocking clear
cycle of all memory locations in the device. The clocking
of the SK pin is not necessary after the device has
entered the self clocking mode. The ready/busy status of
the CAT93C46/56/57/66/86 can be determined by se-
lecting the device and polling the DO pin. Once cleared,
the contents of all memory bits return to a logical “1”
state.
Write All
Upon receiving a WRAL command and data, the CS
(Chip Select) pin must be deselected for a minimum of
t
CSMIN
. The falling edge of CS will start the self clocking
data write to all memory locations in the device. The
clocking of the SK pin is not necessary after the device
has entered the self clocking mode. The ready/busy
status of the CAT93C46/56/57/66/86 can be determined
by selecting the device and polling the DO pin. It is not
necessary for all memory locations to be cleared before
the WRAL command is executed.
93C46/56/57/66/86 F06
Figure 4. Erase Instruction Timing
SK
CS
DI
DO
STANDBY
HIGH-Z
HIGH-Z
1
AN
AN-1
BUSY
READY
STATUS VERIFY
tSV
tHZ
tEW
tCS
1
1
A0
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CAT93C46_07 | 制造商:CATALYST 制造商全稱:Catalyst Semiconductor 功能描述:1-Kb Microwire Serial EEPROM |
| CAT93C4611 | 制造商:CATALYST 制造商全稱:Catalyst Semiconductor 功能描述:Supervisory Circuits with Microwire Serial CMOS E2PROM, Precision Reset Controller and Watchdog Timer |
| CAT93C4612 | 制造商:CATALYST 制造商全稱:Catalyst Semiconductor 功能描述:Supervisory Circuits with Microwire Serial CMOS E2PROM, Precision Reset Controller and Watchdog Timer |
| CAT93C4612PI-45TE13 | 制造商:CATALYST 制造商全稱:Catalyst Semiconductor 功能描述:Supervisory Circuits with Microwire Serial CMOS E2PROM, Precision Reset Controller and Watchdog Timer |
| CAT93C4613 | 制造商:CATALYST 制造商全稱:Catalyst Semiconductor 功能描述:Supervisory Circuits with Microwire Serial CMOS E2PROM, Precision Reset Controller and Watchdog Timer |
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