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參數(shù)資料
| 型號： | CAT64LC40ZS-TE7 |
| 英文描述： | 72-Mbit QDR™-II SRAM 4-Word Burst Architecture |
| 中文描述： | SPI串行EEPROM |
| 文件頁數(shù)： | 1/11頁 |
| 文件大?。?/td> | 140K |
| 代理商： | CAT64LC40ZS-TE7 |
1
CS
SK
DI
DO
VCC
RDY/BUSY
RESET
GND
1
2
3
4
8
7
6
5
CS
SK
DI
DO
VCC
RDY/BUSY
RESET
GND
1
2
3
4
8
7
6
5
RDY/BUSY
VCC
CS
SK
RESET
GND
DO
DI
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
CS
SK
DI
DO
VCC
RDY/
BUSY
RESET
GND
1
2
3
4
8
7
6
5
RDY/
BUSY
VCC
CS
SK
RESET
GND
DO
DI
CAT64LC10/20/40
1K/2K/4K-Bit SPI Serial EEPROM
FEATURES
I
SPI bus compatible
I
Low power CMOS technology
I
2.5V to 6.0V operation
I
Self-timed write cycle with auto-clear
I
Hardware reset pin
I
Hardware and software write protection
I
Commercial, industrial and automotive
temperature ranges
I
Power-up inadvertant write protection
I
RDY/
BSY
pin for end-of-write indication
I
1,000,000 program/erase cycles
I
100 year data retention
DESCRIPTION
The CAT64LC10/20/40 is a 1K/2K/4K-bit Serial EEPROM
which is configured as 64/128/256 registers by 16 bits.
Each register can be written (or read) serially by using
the DI (or DO) pin. The CAT64LC10/20/40 is
manufactured using Catalyst’s advanced CMOS
EEPROM floating gate technology. It is designed to
endure 1,000,000 program/erase cycles and has a data
retention of 100 years. The device is available in 8-pin
DIP, SOIC and TSSOP packages.
BLOCK DIAGRAM
PIN CONFIGURATION
DIP Package (P)
SOIC Package (J) TSSOP Package (U)
PIN FUNCTIONS
Pin Name
Function
CS
Chip Select
SK
Clock Input
DI
Serial Data Input
DO
Serial Data Output
V
CC
+2.5V to +6.0V Power Supply
GND
Ground
RESET
Reset
RDY/BUSY
Ready/BUSY Status
2001 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1021, Rev. A
SOIC Package (S) TSSOP Package (UR)
64LC10/20/40 F02
VCC
ADDRESS
DECODER
MEMORY ARRAY
64/128/256 x 16
DATA
REGISTER
MODE DECODE
LOGIC
CLOCK
GENERATOR
OUTPUT
BUFFER
DO
SK
CS
DI
RESET
GND
RDY/BUSY
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