參數(shù)資料
型號(hào): CAT5269W-25TE13
元件分類: 數(shù)字電位計(jì)
英文描述: Dual Digitally Programmable Potentiometers (DPP) with 64 Taps and 2-wire Interface
中文描述: 雙數(shù)字可編程電位計(jì)(民進(jìn)黨)與64個(gè)龍頭和2線接口
文件頁(yè)數(shù): 7/18頁(yè)
文件大小: 95K
代理商: CAT5269W-25TE13
7
CAT5419
Document No. 2115, Rev. F
WRITE OPERATIONS
In the Write mode, the Master device sends the START
condition and the slave address information to the Slave
device. After the Slave generates an acknowledge, the
Master sends the instruction byte that defines the
requested operation of CAT5419. The instruction byte
consist of a four-bit opcode followed by two register
selection bits and two pot selection bits. After receiving
another acknowledge from the Slave, the Master device
transmits the data to be written into the selected register.
The CAT5419 acknowledges once more and the Master
generates the STOP condition, at which time if a non-
volatile data register is being selected, the device begins
an internal programming cycle to non-volatile memory.
While this internal cycle is in progress, the device will not
respond to any request from the Master device.
Acknowledge Polling
The disabling of the inputs can be used to take advantage
of the typical write cycle time. Once the stop condition is
issued to indicate the end of the host's write operation,
the CAT5419 initiates the internal write cycle. ACK
polling can be initiated immediately. This involves issuing
the start condition followed by the slave address. If the
CAT5419 is still busy with the write operation, no ACK
will be returned. If the CAT5419 has completed the write
operation, an ACK will be returned and the host can then
proceed with the next instruction operation.
WRITE PROTECTION
The Write Protection feature allows the user to protect
against inadvertent programming of the non-volatile
data registers. If the
WP
pin is tied to LOW, the data
registers are protected and become read only. Similarly,
WP
pin going LOW after Start will interrupt non-volatile
write to data registers, while
WP
pin going LOW after
internal write cycle has started will have no effect on any
write operation.The CAT5419 will accept both slave
addresses and instructions, but the data registers are
protected from programming by the device
s failure to
send an acknowledge after data is received.
Figure 6. Write Timing
Figure 5. Slave Address Bits
0
1
0
1
A3
A2
A1
A0
CAT5419
*
**
A0, A1, A2 and A3 correspond to pin A0, A1, A2 and A3 of the device.
A0, A1, A2 and A3 must compare to its corresponding hard wired input pins.
S
A
C
K
A
C
K
DR1 WCR DATA
S
T
O
P
P
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
T
A
C
K
SLAVE/DPP
ADDRESS
INSTRUCTION
BYTE
Fixed
Variable
op code
Data Register
Address
Pot/WCR
Address
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