參數(shù)資料
型號: CAT5269
英文描述: 132dB SNR Highest Performance Stereo Audio DAC (H/W Control) 28-SSOP -25 to 85
中文描述: 雙數(shù)字可編程電位計(民進(jìn)黨)與256絲錐和2線接口
文件頁數(shù): 5/15頁
文件大?。?/td> 134K
代理商: CAT5269
5
CAT5269
Document No. 2123, Rev. B
POWER UP TIMING
(1)(2)
Symbol
t
PUR
t
PUW
Parameter
Max.
1
Units
ms
Power-up to Read Operation
Power-up to Write Operation
1
ms
The write cycle is the time from a valid stop condition of a write sequence to the end of the internal program/erase
cycle. During the write cycle, the bus interface circuits are disabled, SDA is allowed to remain high, and the device
does not respond to its slave address.
tHIGH
SCL
SDA IN
SDA OUT
tLOW
tF
tLOW
tR
tBUF
tSU:STO
tSU:DAT
tHD:DAT
tHD:STA
tSU:STA
tAA
tDH
Figure 1. Bus Timing
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specified operation can be initiated.
RELIABILITY CHARACTERISTICS
Symbol
N
END(1)
Parameter
Min.
Max.
Units
Reference Test Method
Endurance
1,000,000
Cycles/Byte
MIL-STD-883, Test Method 1033
T
DR(1)
Data Retention
100
Years
MIL-STD-883, Test Method 1008
V
ZAP(1)
ESD Susceptibility
2000
Volts
MIL-STD-883, Test Method 3015
I
LTH(1)
Latch-Up
100
mA
JEDEC Standard 17
XDCP TIMING
Symbol
t
WRPO
t
WRL
Parameter
Wiper Response Time After Power Supply Stable
Min
5
Max
10
Units
μ
s
μ
s
Wiper Response Time After Instruction Issued
5
10
WRITE CYCLE LIMITS
Symbol
t
WR
Parameter
Write Cycle Time
Max.
5
Units
ms
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