參數(shù)資料
型號: CAT5259YI-50-T2
廠商: ON Semiconductor
文件頁數(shù): 13/15頁
文件大?。?/td> 0K
描述: IC POT DPP 50K 256TAP 24TSSOP
標準包裝: 2,000
接片: 256
電阻(歐姆): 50k
電路數(shù): 4
溫度系數(shù): 標準值 300 ppm/°C
存儲器類型: 非易失
接口: I²C(設(shè)備位址)
電源電壓: 2.5 V ~ 6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 24-TSSOP
包裝: 帶卷 (TR)
CAT5259
http://onsemi.com
7
Acknowledge
After a successful data transfer, each receiving device is
required to generate an acknowledge. The Acknowledging
device pulls down the SDA line during the ninth clock cycle,
signaling that it received the 8 bits of data.
The CAT5259 responds with an acknowledge after
receiving a START condition and its slave address. If the
device has been selected along with a write operation, it
responds with an acknowledge after receiving each 8-bit
byte.
When the CAT5259 is in a READ mode it transmits 8 bits
of data, releases the SDA line, and monitors the line for an
acknowledge. Once it receives this acknowledge, the
CAT5259 will continue to transmit data. If no acknowledge
is sent by the Master, the device terminates data transmission
and waits for a STOP condition.
WRITE OPERATIONS
In the Write mode, the Master device sends the START
condition and the slave address information to the Slave
device. After the Slave generates an acknowledge, the
Master sends the instruction byte that defines the requested
operation of CAT5259. The instruction byte consist of a
four-bit opcode followed by two register selection bits and
two pot selection bits. After receiving another acknowledge
from the Slave, the Master device transmits the data to be
written into the selected register. The CAT5259
acknowledges once more and the Master generates the
STOP condition, at which time if a non-volatile data register
is being selected, the device begins an internal programming
cycle to non-volatile memory. While this internal cycle is in
progress, the device will not respond to any request from the
Master device.
Acknowledge Polling
The disabling of the inputs can be used to take advantage
of the typical write cycle time. Once the stop condition is
issued to indicate the end of the host’s write operation, the
CAT5259 initiates the internal write cycle. ACK polling can
be initiated immediately. This involves issuing the start
condition followed by the slave address. If the CAT5259 is
still busy with the write operation, no ACK will be returned.
If the CAT5259 has completed the write operation, an ACK
will be returned and the host can then proceed with the next
instruction operation.
Write Protection
The Write Protection feature allows the user to protect
against inadvertent programming of the non-volatile data
registers. If the WP pin is tied to LOW, the data registers are
protected and become read only. Similarly, the WP pin is
going low after start will interrupt non-volatile write to data
registers, while WP pin going low after an internal write
cycle has started will have no effect on any write operation.
The CAT5259 will accept both slave addresses and
instructions, but the data registers are protected from
programming by the device’s failure to send an
acknowledge after data is received.
STOP
CONDITION
START
CONDITION
ADDRESS
ACK
8TH BIT
BYTE n
SCL
SDA
Figure 3. Write Cycle Timing
Figure 4. Start/Stop Condition
START CONDITION
SDA
STOP CONDITION
SCL
tWR
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