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參數(shù)資料
| 型號(hào)： | CAT34WC02UI-2.7 |
| 英文描述： | MoBL® 1-Mbit (128K x 8) Static RAM |
| 中文描述： | I2C串行EEPROM的 |
| 文件頁(yè)數(shù)： | 4/10頁(yè) |
| 文件大?。?/td> | 68K |
| 代理商： | CAT34WC02UI-2.7 |
CAT34AC02
4
Doc. No. 1025, Rev. E
FUNCTIONAL DESCRIPTION
The CAT34AC02 supports the SMBus data transmission
protocol. This serial protocol defines any device that
sends data to the bus to be a transmitter and any device
receiving data to be a receiver. Data transfer is controlled
by the Master device which generates the serial clock
and all START and STOP conditions for bus access. The
CAT34AC02 operates as a Slave device. Both the
Master and Slave devices can operate as either
transmitter or receiver, but the Master device controls
which mode is activated. A maximum of 8 devices may
be connected to the bus as determined by the device
address inputs A0, A1, and A2.
PIN DESCRIPTIONS
SCL:
Serial Clock
The CAT34AC02 serial clock input pin is used to clock
all data transfers into or out of the device. This is an input
pin.
SDA:
Serial Data/Address
The CAT34AC02 bidirectional serial data/address pin is
used to transfer data into and out of the device. The SDA
pin is an open drain output and can be wire-ORed with
other open drain or open collector outputs.
A0, A1, A2:
Device Address Inputs
These inputs set device address when cascading multiple
devices. A maximum of eight devices can be cascaded
when using the device.
WP:
Write Protect
This input, when tied to GND, allows write operations to
the entire memory. For CAT34AC02 when this pin is tied
to V
CC
, the entire array of memory is write protected.
When left floating, memory is unprotected.
Figure 3. Start/Stop Timing
Figure 2. Write Cycle Timing
Figure 1. Bus Timing
tHIGH
SCL
SDA IN
SDA OUT
tLOW
tF
tLOW
tR
tBUF
tSU:STO
tSU:DAT
tHD:DAT
tHD:STA
tSU:STA
tAA
tDH
tWR
STOP
CONDITION
START
CONDITION
ADDRESS
ACK
8TH BIT
BYTE n
SCL
SDA
START BIT
SDA
STOP BIT
SCL
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CAT34WC02UI-TE13 | MoBL® 1-Mbit (128K x 8) Static RAM |
| CAT34WC02U-TE13 | MoBL® 1 Mbit (128K x 8) Static RAM |
| CAT34WC02W | EEPROM |
| CAT34WC02W-1.8 | MoBL® 2-Mbit (128K x 16) Static RAM |
| CAT34WC02W-1.8TE13 | MoBL® 2-Mbit (128K x 16) Static RAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CAT34WC02UI-TE13 | 制造商:Catalyst Semiconductor 功能描述:256 X 8 I2C/2-WIRE SERIAL EEPROM, 3500 ns, PDSO8 |
| CAT34WC02UITE13A | 制造商:CATALYST 制造商全稱:Catalyst Semiconductor 功能描述:2-kb I2C Serial EEPROM, Serial Presence Detect |
| CAT34WC02UITE13C | 制造商:CATALYST 制造商全稱:Catalyst Semiconductor 功能描述:2-kb I2C Serial EEPROM, Serial Presence Detect |
| CAT34WC02UITE13E | 制造商:CATALYST 制造商全稱:Catalyst Semiconductor 功能描述:2-kb I2C Serial EEPROM, Serial Presence Detect |
| CAT34WC02U-TE13 | 制造商:ON Semiconductor 功能描述:EEPROM Serial-I2C 2K-Bit 256 x 8 3.3V/5V 8-Pin TSSOP T/R |
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