參數(shù)資料
型號(hào)： CAT34TS02VP2IGT4
廠商： ON Semiconductor
文件頁(yè)數(shù)： 1/21頁(yè)
文件大?。?/td> 194K
描述： IC TEMP SENSOR WITH MEMORY 8TDFN
標(biāo)準(zhǔn)包裝： 4,000
功能： 溫度監(jiān)控系統(tǒng)（傳感器）
傳感器類型： 內(nèi)部
感應(yīng)溫度： -20°C ~ 125°C
精確度： ±3°C
拓?fù)洌?/td> ADC，比較器，寄存器庫(kù)
輸出類型： 2 線串行，I²C?/SMBUS?
輸出警報(bào)： 是
輸出風(fēng)扇： 無(wú)
電源電壓： 3 V ~ 3.6 V
工作溫度： -20°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： 8-WFDFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 8-TDFN（2x3）
包裝： 帶卷 (TR)
?Semiconductor Components Industries, LLC, 2013
July, 2013  Rev. 11
1
Publication Order Number:
CAT34TS02/D
CAT34TS02
Digital Output Temperature
Sensor with On-board SPD
EEPROM
Description
The CAT34TS02 combines a JC42.4 compliant Temperature Sensor
(TS) with 2Kb of Serial Presence Detect (SPD) EEPROM.
The TS measures temperature at least 10 times every second.
Temperature readings can be retrieved by the host via the serial
interface, and are compared to high, low and critical trigger limits
stored into internal registers. Over or under limit conditions can be
signaled on the opendrain EVENT
 pin.
The integrated 2Kb SPD EEPROM is internally organized as 16
pages of 16 bytes each, for a total of 256 bytes. It features a page write
buffer and supports both the Standard (100 kHz) as well as Fast
(400 kHz) I
2
C protocol.
Write operations to the lower half memory can be inhibited via
software commands. The CAT34TS02 features Permanent, as well as
Reversible Software Write Protection, as defined for DDR3 DIMMs.
Features
" JEDEC JC42.4 Compliant Temperature Sensor
" Temperature Range: 20?/SPAN>C to +125?/SPAN>C
" DDR3 DIMM Compliant SPD EEPROM
" Supply Range: 3.3 V ?/SPAN> 10%
" I
2
C / SMBus Interface
" Schmitt Triggers and Noise Suppression Filters on SCL and SDA
Inputs
" Low Power CMOS Technology
" 2 x 3 x 0.75 mm TDFN Package and 2 x 3 x 0.5 mm UDFN Package
" These Devices are PbFree and are RoHS Compliant
Figure 1. Functional Symbol
SDA
SCL
CAT34TS02
V
CC
V
SS
A
2
, A
1
, A
0
EVENT
http://onsemi.com
PIN CONFIGURATION
SDA
EVENT
V
CC
V
SS
A
2
A
1
A
0
1
See detailed ordering and shipping information in the package
dimensions section on page 21 of this data sheet.
ORDERING INFORMATION
SCL
(Top View)
Device Address Input
A
0
, A
1
, A
2
Serial Data Input/Output
SDA
Serial Clock Input
SCL
Opendrain Event Output
EVENT
Power Supply
V
CC
Ground
V
SS
Function
Pin Name
PIN FUNCTIONS
For the location of Pin 1, please consult the
corresponding package drawing.
TDFN8
VP2 SUFFIX
CASE 511AK
Backside Exposed DAP at V
SS
DAP
MARKING DIAGRAM
GTX
ALL
YM
GTX, TSU = Specific Device Code
A
= Assembly Location Code
LL
= Assembly Lot Number (Last Two Digits)
Y
= Production Year (Last Digit)
M
= Production Month (1  9, O, N, D)
G
= PbFree Package
G
UDFN8
HU4 SUFFIX
CASE 517AZ
TSU
ALL
YM
G
TDFN8
UDFN8
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