
CAT28LV65
6
Doc. No. 1024, Rev. D
ADDRESS
CE
OE
WE
DATA OUT
tAS
DATA IN
DATA VALID
HIGH-Z
tCS
tAH
tCH
tWC
tOEH
tBLC
tDH
tDS
tWP
RDY/BUSY
tOES
tRB
HIGH-Z
HIGH-Z
ADDRESS
CE
OE
WE
tRC
DATA OUT
DATA VALID
DATA VALID
tCE
tOE
tOH
tAA
tOHZ
tHZ
VIH
HIGH-Z
tLZ
tOLZ
Byte Write
A write cycle is executed when both
CE
and
WE
are low,
and
OE
is high. Write cycles can be initiated using either
WE
or
CE
, with the address input being latched on the
falling edge of
WE
or
CE
, whichever occurs last. Data,
conversely, is latched on the rising edge of
WE
or
CE
,
whichever occurs first. Once initiated, a byte write cycle
automatically erases the addressed byte and the new
data is written within 5 ms.
DEVICE OPERATION
Read
Data stored in the CAT28LV65 is transferred to the data
bus when
WE
is held high, and both
OE
and
CE
are held
low. The data bus is set to a high impedance state when
either
CE
or
OE
goes high. This 2-line control architec-
ture can be used to eliminate bus contention in a system
environment.
Figure 4. Byte Write Cycle [WE Controlled]
Figure 3. Read Cycle