參數(shù)資料
型號: CAT28LV64JA-25T
元件分類: PROM
英文描述: 8K X 8 EEPROM 3V, 250 ns, PDSO28
封裝: SOIC-28
文件頁數(shù): 9/12頁
文件大?。?/td> 527K
代理商: CAT28LV64JA-25T
CAT28LV64
6
Doc. No. 1010, Rev. D
Doc. No. 1010, Rev. A
ADDRESS
CE
OE
WE
DATA OUT
tAS
DATA IN
DATA VALID
HIGH-Z
tCS
tAH
tCH
tWC
tOEH
tBLC
tDH
tDS
tOES
tWP
Byte Write
A write cycle is executed when both CE and WE are low,
and OE is high. Write cycles can be initiated using either
WE or CE, with the address input being latched on the
falling edge of WE or CE, whichever occurs last. Data,
conversely, is latched on the rising edge of WE or CE,
whichever occurs first. Once initiated, a byte write cycle
automatically erases the addressed byte and the new
data is written within 5 ms.
Figure 3. Read Cycle
Figure 4. Byte Write Cycle [WE Controlled]
DEVICE OPERATION
Read
Data stored in the CAT28LV64 is transferred to the data
bus when WE is held high, and both OE and CE are held
low. The data bus is set to a high impedance state when
either CE or OE goes high. This 2-line control architecture
can be used to eliminate bus contention in a system
environment.
ADDRESS
CE
OE
WE
tRC
DATA OUT
DATA VALID
tCE
tOE
tOH
tAA
tOHZ
tHZ
VIH
HIGH-Z
tLZ
tOLZ
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