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參數(shù)資料
| 型號(hào)： | CAT25C64Y20I |
| 元件分類： | PROM |
| 英文描述： | 8K X 8 SPI BUS SERIAL EEPROM, PDSO20 |
| 封裝： | LEAD FREE AND HALOGEN FREE, TSSOP-20 |
| 文件頁數(shù)： | 8/11頁 |
| 文件大?。?/td> | 69K |
| 代理商： | CAT25C64Y20I |
6
CAT25C32/64
Doc. No. 1001, Rev. G
Figure 2. WREN Instruction Timing
Figure 3. WRDI Instruction Timing
STATUS REGISTER
The Status Register indicates the status of the device.
The
RDY (Ready) bit indicates whether the CAT25C32/
64 is busy with a write operation. When set to 1 a write
cycle is in progress and when set to 0 the device
indicates it is ready. This bit is read only.
The WEL (Write Enable) bit indicates the status of the
write enable latch . When set to 1, the device is in a
Write Enable state and when set to 0 the device is in a
Write Disable state. The WEL bit can only be set by the
WREN instruction and can be reset by the WRDI
instruction.
The BP0 and BP1 (Block Protect) bits indicate which
blocks are currently protected. These bits are set by the
user issuing the WRSR instruction. The user is allowed
to protect quarter of the memory, half of the memory or
the entire memory by setting these bits. Once protected
the user may only read from the protected portion of the
array. These bits are non-volatile.
Note: Dashed Line= mode (1, 1) — — — —
SK
SI
CS
SO
00000
11
0
HIGH IMPEDANCE
SK
SI
CS
SO
00000
10
0
HIGH IMPEDANCE
The WPEN (Write Protect Enable) is an enable bit for the
WP pin. The WP pin and WPEN bit in the status register
control the programmable hardware write protect feature.
Hardware write protection is enabled when
WP is low and
WPEN bit is set to high. The user cannot write to the status
register (including the block protect bits and the WPEN
bit) and the block protected sections in the memory array
when the chip is hardware write protected. Only the
sections of the memory array that are not block protected
can be written. Hardware write protection is disabled
when either WP pin is high or the WPEN bit is zero.
DEVICE OPERATION
Write Enable and Disable
The CAT25C32/64 contains a write enable latch. This
latch must be set before any write operation. The device
powers up in a write disable state when Vcc is applied.
WREN instruction will enable writes (set the latch) to
thedevice. WRDI instruction will disable writes (reset the
latch) to the device. Disabling writes will protect the
device against inadvertent writes.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CAT25C64Y20I-1.8 | 功能描述:電可擦除可編程只讀存儲(chǔ)器 (8kx8) 64K 1.8-6.0 RoHS:否 制造商:Atmel 存儲(chǔ)容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時(shí)鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 |
| CAT25C65L | 功能描述:電可擦除可編程只讀存儲(chǔ)器 (8kx8) 64K 2.5-6.0 RoHS:否 制造商:Atmel 存儲(chǔ)容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時(shí)鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 |
| CAT25C65L-1.8 | 功能描述:電可擦除可編程只讀存儲(chǔ)器 (8kx8) 64K 1.8-6.0 RoHS:否 制造商:Atmel 存儲(chǔ)容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時(shí)鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 |
| CAT25C65LA | 功能描述:電可擦除可編程只讀存儲(chǔ)器 (8kx8) 64K 2.5-6.0 RoHS:否 制造商:Atmel 存儲(chǔ)容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時(shí)鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 |
| CAT25C65LI | 功能描述:電可擦除可編程只讀存儲(chǔ)器 (8kx8) 64K 2.5-6.0 RoHS:否 制造商:Atmel 存儲(chǔ)容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時(shí)鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 |
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