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參數(shù)資料
| 型號(hào)： | CAT25C256Y20-1.8-GT2 |
| 英文描述： | 128K/256K-Bit SPI Serial CMOS EEPROM |
| 中文描述： | 128K/256K-Bit SPI串行EEPROM中的CMOS |
| 文件頁(yè)數(shù)： | 8/12頁(yè) |
| 文件大?。?/td> | 454K |
| 代理商： | CAT25C256Y20-1.8-GT2 |
CAT25C128/256
8
Document No. 1018, Rev. I
properly set. Also, for a successful write operation the
address of the memory location(s) to be programmed
must be outside the protected address field location
selected by the block protection level.
Byte Write
Once the device is in a Write Enable state, the user may
proceed with a write sequence by setting the
CS
low,
issuing a write instruction via the SI line, followed by the
16-bit address (the three Most Significant Bits are don’t
care for 25C256 and four most significant bits are don't
care for 25C128), and then the data to be written.
Programming will start after the
CS
is brought high. Figure
6 illustrates byte write sequence.
During an internal write cycle, all commands will be
ignored except the RDSR (Read Status Register)
instruction.
To read the status register, RDSR instruction should be
sent. The contents of the status register are shifted out
on the SO line. The status register may be read at any
time even during a write cycle. Read sequece is illus-
trated in Figure 4. Reading status register is illustrated in
Figure 5.
WRITE Sequence
The CAT25C128/256 powers up in a Write Disable
state. Prior to any write instructions, the WREN instruc-
tion must be sent to CAT25C128/256. The device goes
into Write enable state by pulling the
CS
low and then
clocking the WREN instruction into CAT25C128/256.
The
CS
must be brought high after the WREN instruction
to enable writes to the device. If the write operation is
initiated immediately after the WREN instruction without
CS
being brought high, the data will not be written to the
array because the write enable latch will not have been
SK
SI
SO
0
0
0
0
0
0
1
1
BYTE ADDRESS*
0
1
2
3
4
5
6
7
8
9
10
20
21
22
23
24
25
26
27
28
29
30
7
6
5
4
3
2
1
0
*Please check the instruction set table for address
CS
OPCODE
DATA OUT
MSB
HIGH IMPEDANCE
Note: Dashed Line= mode (1, 1)
—
— — —
Figure 4. Read Instruction Timing
Figure 5. RDSR Timing
0
1
2
3
4
5
6
7
8
10
9
11
12
13
14
SCK
SI
DATA OUT
MSB
HIGH IMPEDANCE
OPCODE
SO
7
6
5
4
3
2
1
0
CS
0
0
0
0
0
1
0
1
Note: Dashed Line= mode (1, 1)
—
— — —
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| CAT25C128L-1.8-GT2 | 128K/256K-Bit SPI Serial CMOS EEPROM |
| CAT25C128L-1.8-GT3 | 128K/256K-Bit SPI Serial CMOS EEPROM |
| CAT25C128L-1.8T2 | 128K/256K-Bit SPI Serial CMOS EEPROM |
| CAT25C128L-1.8T3 | 128K/256K-Bit SPI Serial CMOS EEPROM |
| CAT25C128LA-1.8-GT2 | 128K/256K-Bit SPI Serial CMOS EEPROM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CAT25C32L | 功能描述:電可擦除可編程只讀存儲(chǔ)器 (4kx8) 32K 2.5-6.0 RoHS:否 制造商:Atmel 存儲(chǔ)容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時(shí)鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 |
| CAT25C32L-1.8 | 功能描述:電可擦除可編程只讀存儲(chǔ)器 (4kx8) 32K 1.8-6.0 RoHS:否 制造商:Atmel 存儲(chǔ)容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時(shí)鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 |
| CAT25C32LA | 功能描述:電可擦除可編程只讀存儲(chǔ)器 (4kx8) 32K 2.5-6.0 RoHS:否 制造商:Atmel 存儲(chǔ)容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時(shí)鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 |
| CAT25C32LI | 功能描述:電可擦除可編程只讀存儲(chǔ)器 (4kx8) 32K 2.5-6.0 RoHS:否 制造商:Atmel 存儲(chǔ)容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時(shí)鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 |
| CAT25C32LI-1.8 | 功能描述:電可擦除可編程只讀存儲(chǔ)器 (4kx8) 32K 1.8-6.0 RoHS:否 制造商:Atmel 存儲(chǔ)容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時(shí)鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 |
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