參數(shù)資料
型號(hào)： CAT25C17AKI-20T
英文描述： 16K-Bit CMOS PARALLEL EEPROM
中文描述： 16K的位CMOS并行的EEPROM
文件頁(yè)數(shù)： 3/10頁(yè)
文件大小： 518K
代理商： CAT25C17AKI-20T
CAT28C17A
3
Doc. No. 1075, Rev. B
*COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation
of the device at these or any other conditions outside of
those listed in the operational sections of this specifica-
tion is not implied. Exposure to any absolute maximum
rating for extended periods may affect device perfor-
mance and reliability.
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ................. –55
°
C to +125
°
C
Storage Temperature....................... –65
°
C to +150
°
C
Voltage on Any Pin with
Respect to Ground
(2)
........... –2.0V to +V
CC
+ 2.0V
V
CC
with Respect to Ground ............... –2.0V to +7.0V
Package Power Dissipation
Capability (Ta = 25
°
C)................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300
°
C
Output Short Circuit Current
(3)
........................ 100 mA
D.C. OPERATING CHARACTERISTICS
V
CC
= 5V
±
10%, unless otherwise specified.
Limits
Symbol
Parameter
Min.
Typ.
Max.
Units
Test Conditions
I
CC
V
CC
Current (Operating, TTL)
35
mA
CE = OE = V
IL
,
f = 1/t
RC
min, All I/O’s Open
I
CCC(5)
V
CC
Current (Operating, CMOS)
25
mA
CE = OE = V
ILC
,
f = 1/t
RC
min, All I/O’s Open
I
SB
V
CC
Current (Standby, TTL)
1
mA
CE = V
IH
, All I/O’s Open
I
SBC(6)
V
CC
Current (Standby, CMOS)
100
μ
A
CE = V
IHC
,
All I/O’s Open
I
LI
Input Leakage Current
–10
10
μ
A
μ
A
V
IN
= GND to V
CC
I
LO
Output Leakage Current
–10
10
V
OUT
= GND to V
CC
,
CE = V
IH
V
IH(6)
High Level Input Voltage
2
V
CC
+0.3
V
V
IL(5)
Low Level Input Voltage
–0.3
0.8
V
V
OH
High Level Output Voltage
2.4
V
I
OH
= –400
μ
A
V
OL
Low Level Output Voltage
0.4
V
I
OL
= 2.1mA
V
WI
Write Inhibit Voltage
3.0
V
RELIABILITY CHARACTERISTICS
Symbol
Parameter
Min.
Max.
Units
Test Method
N
END(1)
Endurance
10,000
Cycles/Byte
MIL-STD-883, Test Method 1033
T
DR(1)
Data Retention
10
Years
MIL-STD-883, Test Method 1008
V
ZAP(1)
ESD Susceptibility
2000
Volts
MIL-STD-883, Test Method 3015
I
LTH(1)(4)
Latch-Up
100
mA
JEDEC Standard 17
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is V
CC
+0.5V, which may overshoot to V
CC
+2.0V for periods of less than 20 ns.
(3) Output shorted for no more than one second. No more than one output shorted at a time.
(4) Latch-up protection is provided for stresses up to 100mA on address and data pins from –1V to V
CC
+1V.
(5) V
ILC
= –0.3V to +0.3V.
(6) V
IHC
= V
CC
–0.3V to V
CC
+0.3V.
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