參數(shù)資料
    型號(hào): CAT25C09VITE13
    元件分類: EEPROM
    英文描述: 1K/2K/4K/8K/16K SPI Serial CMOS EEPROM
    中文描述: 1K/2K/4K/8K/16K SPI 串行 互補(bǔ)型金屬氧化物 電可擦可編程只讀存儲(chǔ)器
    文件頁數(shù): 9/12頁
    文件大?。?/td> 315K
    代理商: CAT25C09VITE13
    DsconinuedPats
    HIGH IMPEDANCE
    9
    CAT25C11/03/05/09/17
    Doc. No. 1017, Rev. L
    2005 by Catalyst Semiconductor, Inc.
    Characteristics subject to change without notice
    Figure 7. WRSR Instruction Timing
    DESIGN CONSIDERATIONS
    The CAT25C11/03/05/09/17 powers up in a write dis-
    able state and in a low power standby mode. A WREN
    instruction must be issued to perform any writes to the
    device after power up. Also,on power up
    CS
    should be
    brought low to enter a ready state and receive an
    instruction. After a successful byte/page write or status
    register write the CAT25C11/03/05/09/17 goes into a
    write disable mode.
    CS
    must be set high after the proper
    number of clock cycles to start an internal write cycle.
    Access to the array during an internal write cycle is
    ignored and programming is continued. On power up,
    SO is in a high impedance. If an invalid op code is
    Figure 8. Page Write Instruction Timing
    0
    1
    2
    3
    4
    5
    6
    7
    8
    10
    9
    11
    12
    13
    14
    SCK
    SI
    MSB
    HIGH IMPEDANCE
    DATA IN
    15
    SO
    CS
    7
    6
    5
    4
    3
    2
    1
    0
    0
    0
    0
    0
    0
    0
    0
    1
    OPCODE
    Note: Dashed Line= mode (1, 1)
    – – –
    Note: Dashed Line= mode (1, 1)
    received, no data will be shifted into the CAT25C11/03/
    05/09/17, and the serial output pin (SO) will remain in a
    high impedance state until the falling edge of
    CS
    is
    detected again.
    When powering down, the supply should be taken down
    to 0V, so that the CAT25C11/03/05/09/17 will be reset
    when power is ramped back up. If this is not possible,
    then, following a brown-out episode, the CAT25C11/
    03/05/09/17 can be reset by refreshing the contents of
    the Status Register (See Application Note AN10).
    SK
    SI
    SO
    0
    0
    0
    0
    X*
    0
    1
    0
    Data
    Byte 1
    0
    1
    2
    3
    4
    5
    6
    7
    8
    21
    22
    23 24-31
    32-39
    Data
    Byte 2
    Data
    Byte 3
    Data Byte N
    7..1
    CS
    OPCODE
    0
    24+(N-1)x8-1..24+(N-1)x8 24+Nx8-1
    DATA IN
    BYTE ADDRESS*
    *Please check the Byte Address Table.
    *X = 0 for CAT25C11, CAT25C03, CAT25C09 and CAT25C17; X = A8 for CAT25C05
    AN
    A0
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