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參數資料
| 型號： | CAT25020S |
| 英文描述： | 16-Bit Buffer/Driver With 3-State Outputs 48-TSSOP -40 to 85 |
| 中文描述： | 1K/2K/4K SPI串行EEPROM中的CMOS |
| 文件頁數： | 5/11頁 |
| 文件大?。?/td> | 73K |
| 代理商： | CAT25020S |
5
CAT25010/20/40
Doc. No. 1006, Rev. L
Status Register Bits
BP1
0
Array Address
Protected
None
Protection
BP0
0
No Protection
0
1
25010: 60-7F
25020: C0-FF
25040: 180-1FF
Quarter Array Protection
1
0
25010: 40-7F
25020: 80-FF
25040: 100-1FF
Half Array Protection
1
1
25010: 00-7F
25020: 00-FF
25040: 000-1FF
Full Array Protection
BLOCK PROTECTION BITS
7
6
5
4
3
2
1
0
1
1
1
1
BP1
BP0
WEL
RDY
STATUS REGISTER
clock for SPI modes (0,0 & 1,1).
SCK:
Serial Clock
SCK is the serial clock pin. This pin is used to synchronize
the communication between the microcontroller and the
CAT25010/20/40. Opcodes, byte addresses, or data
present on the SI pin are latched on the rising edge of the
SCK. Data on the SO pin is updated on the falling edge
of the SCK for SPI modes (0,0 & 1,1) .
CS
:
Chip Select
CS
is the Chip select pin.
CS
low enables the CAT25010/
20/40 and
CS
high disables the CAT25010/20/40.
CS
high takes the SO output pin to high impedance and
forces the devices into a Standby Mode (unless an
internal write operation is underway) The CAT25010/
20/40 draws ZERO current in the Standby mode. A high
to low transition on
CS
is required prior to any sequence
being initiated. A low to high transition on
CS
after a valid
write sequence is what initiates an internal write cycle.
WP
:
Write Protect
WP
is the Write Protect pin. The Write Protect pin will
allow normal read/write operations when held high.
When
WP
is tied low all write operations are inhibited.
WP
held low while
CS
is low will interrupt a write to the
CAT25010/20/40. If the internal write cycle has already
been initiated,
WP
going low will have no effect on any
write operation. Figure 10 illustrates the
WP
timing
sequence during a write operation.
HOLD
:
Hold
The
HOLD
pin is used to pause transmission to the
CAT25010/20/40 while in the middle of a serial sequence
without having to re-transmit entire sequence at a later
time. To pause,
HOLD
must be brought low while SCK
is low. The SO pin is in a high impedance state during
the time the part is paused, and transitions on the SI pins
will be ignored. To resume communication,
HOLD
is
brought high, while SCK is low. (
HOLD
should be held
high any time this function is not being used.)
HOLD
may
be tied high directly to V
CC
or tied to V
CC
through a
resistor. Figure 9 illustrates hold timing sequence.
相關PDF資料 |
PDF描述 |
|---|---|
| CAT25020SA | 16-Bit Buffer/Driver With 3-State Outputs 48-TSSOP -40 to 85 |
| CAT25020SE | 16-Bit Buffer/Driver With 3-State Outputs 48-TVSOP -40 to 85 |
| CAT25020SI | 16-Bit Buffer/Driver With 3-State Outputs 48-TVSOP -40 to 85 |
| CAT25020U | 16-Bit Buffer/Driver With 3-State Outputs 48-SSOP -40 to 85 |
| CAT25020UA | 16-Bit Buffer/Driver With 3-State Outputs 48-TSSOP -40 to 85 |
相關代理商/技術參數 |
參數描述 |
|---|---|
| CAT25020S-1.8 | 功能描述:電可擦除可編程只讀存儲器 (256x8) 2K 1.8-6.0 RoHS:否 制造商:Atmel 存儲容量:2 Kbit 組織:256 B x 8 數據保留:100 yr 最大時鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-8 |
| CAT25020SA | 功能描述:電可擦除可編程只讀存儲器 (256x8) 2K 2.5-6.0 RoHS:否 制造商:Atmel 存儲容量:2 Kbit 組織:256 B x 8 數據保留:100 yr 最大時鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-8 |
| CAT25020SI | 功能描述:電可擦除可編程只讀存儲器 (256x8) 2K 2.5-6.0 RoHS:否 制造商:Atmel 存儲容量:2 Kbit 組織:256 B x 8 數據保留:100 yr 最大時鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-8 |
| CAT25020SI-1.8 | 功能描述:電可擦除可編程只讀存儲器 (256x8) 2K 1.8-6.0 RoHS:否 制造商:Atmel 存儲容量:2 Kbit 組織:256 B x 8 數據保留:100 yr 最大時鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-8 |
| CAT25020SI-TE13 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Catalyst Semiconductor 功能描述: |
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