1
CAT24WC03/05/09/17
2K/4K/8K/16K-Bit Serial E
2
PROM
* Catalyst Semiconductor is licensed by Philips Corporation to carry the I
2
C Bus Protocol.
PIN CONFIGURATION
BLOCK DIAGRAM
PIN FUNCTIONS
Pin Name
Function
A0, A1, A2
Device Address Inputs
SDA
Serial Data/Address
SCL
Serial Clock
WP
Write Protect
V
CC
+1.8V to +6.0V Power Supply
V
SS
Ground
DIP Package (P)
24WCXX F03
TSSOP Package (U)
(** Available for 24WC03 only)
FEATURES
I
400 KHZ I
2
C Bus Compatible*
I
1.8 to 6.0Volt Operation
I
Low Power CMOS Technology
I
Write Protect Feature
–Top 1/2 Array Protected When WP at V
IH
I
16-Byte Page Write Buffer
I
Self-Timed Write Cycle with Auto-Clear
I
1,000,000 Program/Erase Cycles
I
100 Year Data Retention
I
8-pin DIP, 8-pin SOIC and 8-pin TSSOP Package
I
Commercial, Industrial and Automotive
Temperature Ranges
DESCRIPTION
The CAT24WC03/05/09/17 is a 2K/4K/8K/16K-bit Serial
CMOS E
2
PROM internally organized as 256/512/1024/
2048 words of 8 bits each. Catalyst’s advanced CMOS
technology substantially reduces device power require-
ments. The CAT24WC03/05/09/17 features a 16-byte
page write buffer. The device operates via the I
2
C bus
serial interface, has a special write protection feature,
and is available in 8-pin DIP or 8-pin SOIC
1999 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Preliminary
DOUT
ACK
SENSE AMPS
SHIFT REGISTERS
CONTROL
LOGIC
WORD ADDRESS
BUFFERS
START/STOP
LOGIC
STATE COUNTERS
SLAVE
ADDRESS
COMPARATORS
E
2
PROM
VCC
EXTERNAL LOAD
COLUMN
DECODERS
XDEC
DATA IN STORAGE
HIGH VOLTAGE/
TIMING CONTROL
VSS
WP
SCL
A0
A1
A2
SDA
Doc. No. 25063-00 2/98 S-1
8
7
6
5
VCC
WP
SCL
SDA
A2
A0
A1
SS
1
2
3
4
VSS
A2
A0
A1
VSS
A0
A1
A2
VCC
WP
SCL
SDA
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
VSS
VCC
WP
SCL
SDA
SOIC Package (J)
