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參數(shù)資料
| 型號： | CAT24FC64GYI-REV-D |
| 元件分類： | PROM |
| 英文描述： | 8K X 8 I2C/2-WIRE SERIAL EEPROM, PDSO8 |
| 封裝： | ROHS COMPLIANT, TSSOP-8 |
| 文件頁數(shù)： | 4/10頁 |
| 文件大?。?/td> | 628K |
| 代理商： | CAT24FC64GYI-REV-D |
Discontinued
Part
CAT24FC64
3
Doc No. 1046, Rev. K
2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Note:
(1) AC measurement conditions:
RL (connects to VCC): 0.3VCC to 0.7 VCC
Input rise and fall times: < 50ns
Input and output timing reference voltages: 0.5 VCC
(2) This parameter is tested initially and after a design or process change that affects the parameter.
(3) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
The write cycle time is the time from a valid stop
condition of a write sequence to the end of the internal
program/erase cycle. During the write cycle, the bus
interface circuits are disabled, SDA is allowed to remain
high, and the device does not respond to its slave
address.
A.C. CHARACTERISTICS
VCC = +2.5V to +5.5V, unless otherwise specified
Output Load is 1 TTL Gate and 100pF
Read & Write Cycle Limits
Power-Up Timing (2)(3)
Symbol
Parameter
Min
Typ
Max
Units
tPUR
Power-Up to Read Operation
100
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tPUW
Power-Up to Write Operation
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