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參數(shù)資料
| 型號： | CAT24FC32AJTE13 |
| 英文描述： | 32K-Bit Fast Mode I2C Serial CMOS EEPROM |
| 中文描述： | 32K的位快速模式I2C串行CMOS EEPROM的 |
| 文件頁數(shù)： | 7/12頁 |
| 文件大?。?/td> | 74K |
| 代理商： | CAT24FC32AJTE13 |
CAT24FC32A
7
Doc. No. 1048, Rev. F
FUNCTIONAL DESCRIPTION
The CAT24FC32A supports the I
2
C Bus data
transmission protocol. This Inter-Integrated Circuit Bus
protocol defines any device that sends data to the bus to
be a transmitter and any device receiving data to be a
receiver. The transfer is controlled by the Master device
which generates the serial clock and all START and
STOP conditions for bus access. The CAT24FC32A
operates as a Slave device. Both the Master device and
Slave device can operate as either transmitter or receiver,
but the Master device controls which mode is activated.
I
2
C Bus Protocol
The features of the I2C bus protocol are defined as
follows:
(1) Data transfer may be initiated only when the bus is
not busy.
(2) During a data transfer, the data line must remain
stable whenever the clock line is high. Any changes
in the data line while the clock line is high will be
interpreted as a START or STOP condition (Figure
6).
START Condition
The START condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of
SDA when SCL is HIGH. The CAT24FC32A monitors
the SDA and SCL lines and will not respond until this
condition is met.
STOP Condition
A LOW to HIGH transition of SDA when SCL is HIGH
determines the STOP condition. All operations must end
with a STOP condition.
DEVICE ADDRESSING
After the bus Master sends a START condition, a slave
address byte is required to enable the CAT24FC32A for
a read or write operation (Figure 7). The four most
significant bits of the 8-bit slave address are fixed as
binary 1010. The CAT24FC32A uses the next three bits
as address bits. The address bits A2, A1 and A0 are
used to select which device is accessed from maximum
eight devices on the same bus. These bits must compare
to their hardwired input pins. The last bit of the slave
address specifies whether a read or write operation is to
be performed. When this bit is set to “1”, a read operation
is initiated, and when set to “0”, a write operation is
selected.
Following the START condition and the slave address
byte, the CAT24FC32A monitors the bus and responds
with an acknowledge (on the SDA line) when its address
matches the transmitted slave address. The
CAT24FC32A then performs a read or write operation
depending on the state of the R/W bit.
Figure 6. Start/Stop Timing
START BIT
SDA
STOP BIT
SCL
1
0
1
0
A2
A1
A0
R/W
Figure 7. Slave Address Bits
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CAT24FC32AKTE13 | 32K-Bit Fast Mode I2C Serial CMOS EEPROM |
| CAT24FC32A | LM5102 High Voltage Half-Bridge Gate Driver with Programmable Delay; Package: LLP; No of Pins: 10 |
| CAT24FC32ALTE13 | LM5102 High Voltage Half-Bridge Gate Driver with Programmable Delay; Package: LLP; No of Pins: 10 |
| CAT24FC32AXTE13 | LM5104 High Voltage Half-Bridge Gate Driver with Adaptive Delay; Package: SOIC NARROW; No of Pins: 8 |
| CAT24FC32AYTE13 | ER 2C 2#8 SKT PLUG |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CAT24FC64LI | 制造商:Rochester Electronics LLC 功能描述: 制造商:Catalyst Semiconductor 功能描述: |
| CAT24FC64WI-TE13 | 制造商:Catalyst Semiconductor 功能描述: |
| CAT24FC64YI | 制造商:Rochester Electronics LLC 功能描述: 制造商:Catalyst Semiconductor 功能描述: |
| CAT24FC64YI-TE13 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Catalyst Semiconductor 功能描述: |
| CAT24G | 制造商:Semiconductors 功能描述: |
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