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參數(shù)資料
| 型號： | CAT22C10L-20-TE13 |
| 英文描述： | 256-Bit Nonvolatile CMOS Static RAM |
| 中文描述： | 256位非易失性的CMOS靜態(tài)RAM |
| 文件頁數(shù)： | 7/10頁 |
| 文件大小： | 514K |
| 代理商： | CAT22C10L-20-TE13 |
CAT22C10
7
Doc. No. 1082, Rev. O
mended.
Write
With the chip enabled and the nonvolatile functions
inhibited, the Write Enable (
WE
) pin will select the write
mode when driven to a low level. In this mode, the
address must be supplied for the byte being written.
After the set-up time (t
AS
), the input data must be
Figure 2. Write Cycle Timing
Figure 3. Early Write Cycle Timing
supplied to pins I/O
0
–I/O
3
. When these conditions, in-
cluding the write pulse width time (t
WP
) are met, the data
will be written to the specified location in the Static RAM.
A write function may also be initiated from the standby
mode by driving
WE
low, inhibiting the nonvolatile func-
tions, supplying valid addresses, and then taking
CS
low
and supplying input data.
tWC
tAS
tWR
DATA VALID
CS
DATA IN
ADDRESS
WE
tWP
tDW
tCW
tDH
DATA OUT
HIGH-Z
tWC
tAS
tWR
DATA VALID
CS
DATA IN
ADDRESS
WE
tWP
tDW
tCW
tDH
DATA OUT
tWZ
tOW
HIGH-Z
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CAT22C10L-30-TE13 | 256-Bit Nonvolatile CMOS Static RAM |
| CAT22C10LA-20-TE13 | 256-Bit Nonvolatile CMOS Static RAM |
| CAT22C10LA-30-TE13 | 256-Bit Nonvolatile CMOS Static RAM |
| CAT22C10LI-20-TE13 | 256-Bit Nonvolatile CMOS Static RAM |
| CAT22C10LI-30-TE13 | 256-Bit Nonvolatile CMOS Static RAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CAT22C10L-30 | 制造商:ON Semiconductor 功能描述:256-BIT N V CMOS STATIC RAM - Rail/Tube |
| CAT22C10L-30-TE13 | 制造商:CATALYST 制造商全稱:Catalyst Semiconductor 功能描述:256-Bit Nonvolatile CMOS Static RAM |
| CAT22C10LA-20-TE13 | 制造商:CATALYST 制造商全稱:Catalyst Semiconductor 功能描述:256-Bit Nonvolatile CMOS Static RAM |
| CAT22C10LA-30-TE13 | 制造商:CATALYST 制造商全稱:Catalyst Semiconductor 功能描述:256-Bit Nonvolatile CMOS Static RAM |
| CAT22C10LE20 | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:256-Bit Nonvolatile CMOS Static RAM |
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