參數(shù)資料
型號: CAT1321ZD2I-30SOIC
英文描述: Supervisory Circuits with I2C Serial 32K CMOS EEPROM
中文描述: 監(jiān)控電路,帶有I2C串行EEPROM中的CMOS 32K的
文件頁數(shù): 5/18頁
文件大小: 496K
代理商: CAT1321ZD2I-30SOIC
5
Advance Information
CAT1320, CAT1321
Doc No. 25085, Rev. 00
RESET CIRCUIT A.C. CHARACTERISTICS
Notes:
1.
2.
3.
4.
5.
6.
Test Conditions according to
AC Test Conditions
table.
Power-up, Input Reference Voltage V
CC
= V
TH
, Reset Output Reference Voltage and Load according to
AC Test Conditions
Table
Power-Down, Input Reference Voltage V
CC
= V
TH
, Reset Output Reference Voltage and Load according to
AC Test Conditions
Table
V
CC
Glitch Reference Voltage = V
THmin
; Based on characterization data
This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested.
t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specified memory operation can be initiated.
AC TEST CONDITIONS
RELIABILITY CHARACTERISTICS
Symbol
N
END(1)
Parameter
Reference Test Method
Min
Max
Units
Endurance
MIL-STD-883, Test Method 1033
1,000,000
Cycles/Byte
T
DR(1)
Data Retention
MIL-STD-883, Test Method 1008
100
Years
V
ZAP(1)
ESD Susceptibility
MIL-STD-883, Test Method 3015
2000
Volts
I
LTH(1)(2)
Latch-Up
JEDEC Standard 17
100
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Notes:
1.
2.
This parameter is tested initially and after a design or process change that affects the parameter. Not 100% tested.
Latch-up protection is provided for stresses up to 100mA on input and output pins from -1V to V
CC
+ 1V.
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