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參數(shù)資料
| 型號(hào)： | CAT1162LI-25 |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 電源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDIP8 |
| 封裝： | 0.300 INCH, ROHS COMPLIANT, PLASTIC, MS-001, DIP-8 |
| 文件頁數(shù)： | 8/14頁 |
| 文件大?。?/td> | 188K |
| 代理商： | CAT1162LI-25 |
CAT1161, CAT1162
2007 Catalyst Semiconductor, Inc.
3
Doc. No. 3002 Rev. F
Characteristics subject to change without notice
D.C. OPERATING CHARACTERISTICS
VCC = 2.7V to 6V, unless otherwise specified.
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
ICC
Power Supply Current
fSCL = 100 KHz
3
mA
VCC = 3.3V
40
A
ISB
Standby Current
VCC = 5
50
A
ILI
Input Leakage Current
VIN = GND or VCC
2
A
ILO
Output Leakage Current
VIN = GND or VCC
10
A
VIL
Input Low Voltage
-1
VCC x 0.3
V
VIH
Input High Voltage
VCC x 0.7
VCC + 0.5
V
VOL1
Output Low Voltage (SDA)
IOL = 3 mA, VCC = 3.0V
0.4
V
CAPACITANCE
TA = 25C, f = 1.0 MHz, VCC = 5V
Symbol
Test
Conditions
Max
Units
CI/O
(1)
Input/Output Capacitance (SDA)
VI/O = 0V
8
pF
CIN
(1)
Input Capacitance (SCL)
VIN = 0V
6
pF
A.C. CHARACTERISTICS
VCC = 2.7V to 6.0V unless otherwise specified. Output Load is 1 TTL Gate and 100pF.
Symbol
Parameter
Min
Max
Min
Max
Units
FSCL
Clock Frequency
100
400
kHz
TI
(1)
Noise Suppresion Time Constant at SCL, SDA Inputs
200
ns
tAA
SLC Low to SDA Data Out and ACK Out
3.5
1
s
tBUF
(1)
Time the Bus Must be Free Before a New Transmission
Can Start
4.7
1.2
s
tHD:STA
Start Condition Hold Time
4
0.6
s
tLOW
Clock Low Period
4.7
1.2
s
tHIGH
Clock High Period
4
0.6
s
tSU:STA
Start Condition Setup Time (for a Repeated Start Condition)
4.7
0.6
s
tHD:DAT
Data in Hold Time
0
ns
tSU:DAT
Data in Setup Time
50
ns
tR
(1)
SDA and SCL Rise Time
1
0.3
s
tF
(1)
SDA and SCL Fall Time
300
ns
tSU:STO
Stop Condition Setup Time
4
0.6
s
tDH
Data Out Hold Time
100
ns
POWER-UP TIMING
(1)(2)
Symbol
Parameter
Max
Units
tPUR
Power-up to Read Operation
1
ms
tPUW
Power-up to Write Operation
1
ms
Notes:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) tPUR and tPUW are the delays required from the time VCC is stable until the specific operation can be initiated.
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