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| 型號(hào)： | CAT1162J-30 |
| 英文描述： | 4A SCRS |
| 中文描述： | I2C串行EEPROM，帶有監(jiān)控功能 |
| 文件頁(yè)數(shù)： | 2/12頁(yè) |
| 文件大小： | 71K |
| 代理商： | CAT1162J-30 |
10
CAT1161/2
Doc. No. 3002, Rev. C
Immediate/Current Address Read
The CAT1161/2 address counter contains the address
of the last byte accessed, incremented by one. In other
words, if the last READ or WRITE access was to
address N, the READ immediately following would access
data from address N+1. For all devices, N=E=2047. The
counter will wrap around to Zero and continue to clock
out valid data for the 16K devices. After the CAT1161/
2 receives its slave address information (with the R/
W bit
set to one), it issues an acknowledge, then transmits the
8-bit byte requested. The master device does not send
an acknowledge, but will generate a STOP condition.
Selective/Random Read
Selective/Random READ operations allow the Master
device to select at random any memory location for a
READ operation. The Master device first performs a
‘dummy’ write operation by sending the START condition,
slave address and byte addresses of the location it
wishes to read. After the CAT1161/2 acknowledges, the
Master device sends the START condition and the slave
address again, this time with the R/
W bit set to one. The
CAT1161/2 then responds with its acknowledge and
sends the 8-bit byte requested. The master device does
not send an acknowledge but will generate a STOP
condition.
Sequential Read
The Sequential READ operation can be initiated by
either the Immediate Address READ or Selective READ
operations. After the CAT1161/2 sends the inital 8-bit
byte requested, the Master will responds with an
acknowledge which tells the device it requires more
data. The CAT1161/2 will continue to output an 8-bit
byte for each acknowledge, thus sending the STOP
condition.
The data being transmitted from the CAT1161/2 is
outputted sequentially with data from address N followed
by data from address N+1. The READ operation address
counter increments all of the CAT1161/2 address bits
so that the entire memory array can be read during one
operation. If more than E (where E=2047 for the
CAT1161/162) bytes are read out, the counter will ‘wrap
around’ and continue to clock out data bytes.
SLAVE
ADDRESS
S
A
C
K
N
O
A
C
K
S
T
O
P
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
T
BYTE
ADDRESS (n)
S
A
C
K
DATA n
SLAVE
ADDRESS
A
C
K
S
T
A
R
T
Figure 10. Selective Read Timing
BUS ACTIVITY:
MASTER
SDA LINE
DATA n+x
DATA n
A
C
K
A
C
K
DATA n+1
A
C
K
S
T
O
P
N
O
A
C
K
DATA n+2
A
C
K
P
SLAVE
ADDRESS
Figure 11. Sequential Read Timing
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| CAT1162J-42 | 0.8A TRIACS |
| CAT1162J-45 | 1 A triacs |
| CAT1162JI-25 | 1 A triacs |
| CAT1162JI-28 | I2C Serial EEPROM with Supervisory Features |
| CAT1162JI-30 | 4 A triacs |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CAT1162J-42 | 功能描述:監(jiān)控電路 16K I2C Mem w/Reset RoHS:否 制造商:STMicroelectronics 監(jiān)測(cè)電壓數(shù): 監(jiān)測(cè)電壓: 欠電壓閾值: 過(guò)電壓閾值: 輸出類型:Active Low, Open Drain 人工復(fù)位:Resettable 監(jiān)視器:No Watchdog 電池備用開關(guān):No Backup 上電復(fù)位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
| CAT1162J42TE13 | 制造商:ON Semiconductor 功能描述:Processor Supervisor 3V/3.3V/5V 8-Pin SOIC N T/R |
| CAT1162J-45 | 功能描述:監(jiān)控電路 16K I2C Mem w/Reset RoHS:否 制造商:STMicroelectronics 監(jiān)測(cè)電壓數(shù): 監(jiān)測(cè)電壓: 欠電壓閾值: 過(guò)電壓閾值: 輸出類型:Active Low, Open Drain 人工復(fù)位:Resettable 監(jiān)視器:No Watchdog 電池備用開關(guān):No Backup 上電復(fù)位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
| CAT1162J-45 TE13 | 制造商:ON Semiconductor 功能描述:Processor Supervisor 3V/3.3V/5V 8-Pin SOIC N T/R |
| CAT1162JI-28 | 功能描述:監(jiān)控電路 16K I2C Mem w/Reset RoHS:否 制造商:STMicroelectronics 監(jiān)測(cè)電壓數(shù): 監(jiān)測(cè)電壓: 欠電壓閾值: 過(guò)電壓閾值: 輸出類型:Active Low, Open Drain 人工復(fù)位:Resettable 監(jiān)視器:No Watchdog 電池備用開關(guān):No Backup 上電復(fù)位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
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