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參數資料
| 型號： | CAT1161PI-45TE13 |
| 英文描述： | Supervisory Circuits with I2C Serial CMOS EEPROM, Precision Reset Controller and Watchdog Timer |
| 中文描述： | 監(jiān)控電路，帶有I2C串行CMOS EEPROM的，精密復位控制器和看門狗定時器 |
| 文件頁數： | 5/12頁 |
| 文件大?。?/td> | 69K |
| 代理商： | CAT1161PI-45TE13 |
5
CAT1161/2
Doc No. 3002, Rev. D
PIN DESCRIPTIONS
WP:
If the pin is tied to V
CC
the entire memory array
becomes Write Protected (READ only). When the pin
is tied to GND or left floating normal read/write
operations are allowed to the device.
WRITE PROTECT
RESET/
These are open drain pins and can be used as reset
trigger inputs. By forcing a reset condition on the pins
the device will initiate and maintain a reset condition.
The RESET pin must be connected through a pull-
down resistor, and the
RESET
pin must be connected
through a pull-up resistor.
RESET
: RESET I/O
SDA:
The bidirectional serial data/address pin is used to
transfer all data into and out of the device. The SDA
pin is an open drain output and can be wire-ORed
with other open drain or open collector outputs.
SERIAL DATA ADDRESS
If there is no transition on the SDA for more than 1.6
seconds, the watchdog timer times out.
SCL:
Serial clock input.
SERIAL CLOCK
DEVICE OPERATION
Reset Controller Description
The CAT1161/2 precision RESET controller ensures
correct system operation during brownout and power
up/down conditions. It is configured with open drain
RESET outputs. During power-up, the RESET outputs
remain active until V
CC
reaches the V
TH
threshold and will
continue driving the outputs for approximately 200ms (t
PURST
)
after reaching V
TH
. After the t
PURST
timeout interval, the
device will cease to drive the reset outputs. At this point the
reset outputs will be pulled up or down by their respective pull
up/down resistors. During power-down, the RESET outputs
will be active when V
CC
falls below V
TH
. The
RESET
outputs
will be valid so long as V
CC
is >1.0V (V
RVALID
).
The RESET pins are I/Os; therefore, the CAT1161/2 can act
as a signal conditioning circuit for an externally applied
manual reset. The inputs are edge triggered; that is, the
RESET input in the CAT1161/2 will initiate a reset timeout
after detecting a low to high transition and the
RESET
input
will initiate a reset timeout after detecting a high to low
transition.
Watchdog Timer
The Watchdog Timer provides an independent protection for
microcontrollers. During a system failure, the CAT1161will
respond with a reset signal after a time-out interval of 1.6
seconds for a lack of activity. The CAT1161 is designed with
the Watchdog Timer feature on the SDA input. If the
microcontroller does not toggle the SDA input pin within 1.6
seconds, the Watchdog Timer times out. This will generate
a reset condition on reset outputs. The Watchdog Timer is
cleared by any transition on SDA.
As long as the reset signal is asserted, the Watchdog Timer
will not count and will stay cleared.
The CAT1162 does not have a Watchdog.
Figure 1. RESET Output Timing
GLITCH
t
V
CC
PURST
t
PURST
t
RPD
t
RVALID
V
V
TH
RESET
RESET
RPD
t
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