參數(shù)資料
型號： CAT1024ZD4I-42T3
英文描述： Supervisory Circuits with I2C Serial 2k-bit CMOS EEPROM and Manual Reset
中文描述： 監(jiān)控電路，帶有I2C串行的2K位CMOS EEPROM和手動復(fù)位
文件頁數(shù)： 13/20頁
文件大?。?/td> 267K
代理商： CAT1024ZD4I-42T3
CAT1024, CAT1025
2007 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
13
Doc. No. 3008 Rev. N
Immediate/Current Address Read
The CAT1024 and CAT1025 address counter
contains the address of the last byte accessed,
incremented by one. In other words, if the last READ
or WRITE access was to address N, the READ
immediately following would access data from
address N + 1. For N = E = 255, the counter will
wrap around to zero and continue to clock out valid
data. After the CAT1024/1025 receives its slave
address information (with the R/ˉˉ bit set to one), it
issues an acknowledge, then transmits the 8-bit byte
requested. The master device does not send an
acknowledge, but will generate a STOP condition.
Selective/Random Read
Selective/Random READ operations allow the
Master device to select at random any memory
location for a READ operation. The Master device
first performs a ‘dummy’ write operation by sending
the START condition, slave address and byte
addresses of the location it wishes to read. After the
CAT1024 and CAT1025 acknowledges, the Master
device sends the START condition and the slave
address again, this time with the R/ˉˉ bit set to one.
The CAT1024 and CAT1025 then responds with its
acknowledge and sends the 8-bit byte requested.
The master device does not send an acknowledge
but will generate a STOP condition.
Sequential Read
The Sequential READ operation can be initiated by
either the Immediate Address READ or Selective READ
operations. After the CAT1024 and CAT1025 sends the
inital 8-bit byte requested, the Master will responds with
an acknowledge which tells the device it requires more
data. The CAT1024 and CAT1025 will continue to
output an 8-bit byte for each acknowledge, thus sending
the STOP condition.
The data being transmitted from the CAT1024 and
CAT1025 is sent sequentially with the data from
address N followed by data from address N + 1. The
READ operation address counter increments all of the
CAT1024 and CAT1025 address bits so that the entire
memory array can be read during one operation.
Figure 11. Selective Read Timing
Figure 12. Sequential Read Timing
SLAVE
ADDRESS
S
A
C
K
N
O
A
C
K
S
T
O
P
P
BUSACTIVITY:
MASTER
SDA LINE
S
T
A
R
T
BYTE
ADDRESS (n)
S
A
C
K
DATA n
SLAVE
ADDRESS
A
C
K
S
T
A
R
T
BUSACTIVITY:
MASTER
SDA LINE
DATA n+x
DATA n
A
C
K
A
C
K
DATA n+1
A
C
K
S
T
O
P
N
O
A
C
K
DATA n+2
A
C
K
P
SLAVE
ADDRESS
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