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參數(shù)資料
| 型號： | CAT1024LI-25T3 |
| 英文描述： | Supervisory Circuits with I2C Serial 2k-bit CMOS EEPROM and Manual Reset |
| 中文描述： | 監(jiān)控電路，帶有I2C串行的2K位CMOS EEPROM和手動復位 |
| 文件頁數(shù)： | 5/20頁 |
| 文件大?。?/td> | 267K |
| 代理商： | CAT1024LI-25T3 |
CAT1024, CAT1025
2007 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
5
Doc. No. 3008 Rev. N
CAPACITANCE
T
A
= 25oC, f = 1.0MHz, V
CC
= 5V
Symbol
Test
C
OUT
Output Capacitance
C
IN
Input Capacitance
AC CHARACTERISTICS
V
CC
= 2.7V to 5.5V and over the recommended temperature conditions, unless otherwise specified.
Memory Read & Write Cycle
(2)
Test Conditions
V
OUT
= 0V
V
IN
= 0V
Max
8
6
Units
pF
pF
(1)
(1)
Symbol
f
SCL
t
SP
t
LOW
t
HIGH
t
R
t
F
t
HD; STA
t
SU; STA
t
HD; DAT
t
SU; DAT
t
SU; STO
t
AA
t
DH
t
BUF
t
WC
Parameter
Clock Frequency
Input Filter Spike Suppression (SDA, SCL)
Clock Low Period
Clock High Period
SDA and SCL Rise Time
SDA and SCL Fall Time
Start Condition Hold Time
Start Condition Setup Time (for a Repeated Start)
Data Input Hold Time
Data Input Setup Time
Stop Condition Setup Time
SCL Low to Data Out Valid
Data Out Hold Time
Time the Bus must be Free Before a New Transmission Can Start
Write Cycle Time (Byte or Page)
Min
1.3
0.6
0.6
0.6
0
100
0.6
50
1.3
Max
400
100
300
300
900
5
Units
kHz
ns
μs
μs
ns
ns
μs
μs
ns
ns
μs
ns
ns
μs
ms
(1)
(1)
(1)
(3)
Notes:
(1) This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested.
(2) Test Conditions according to “AC Test Conditions” table.
(3) The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the
write cycle, the bus interface circuits are disabled, SDA is allowed to remain high and the device does not respond to its slave address.
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| CAT1024LI-28 | Supervisory Circuits with I2C Serial 2k-bit CMOS EEPROM and Manual Reset |
| CAT1024LI-28-GT2 | Supervisory Circuits with I2C Serial 2k-bit CMOS EEPROM and Manual Reset |
| CAT1024LI-28-GT3 | Supervisory Circuits with I2C Serial 2k-bit CMOS EEPROM and Manual Reset |
| CAT1024LI-28T2 | Supervisory Circuits with I2C Serial 2k-bit CMOS EEPROM and Manual Reset |
| CAT1024LI-28T3 | Supervisory Circuits with I2C Serial 2k-bit CMOS EEPROM and Manual Reset |
相關代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CAT1024LI-25TE13 | 制造商:CATALYST 制造商全稱:Catalyst Semiconductor 功能描述:Supervisory Circuits with I2C Serial 2k-bit CMOS EEPROM and Manual Reset |
| CAT1024LI28 | 功能描述:監(jiān)控電路 2K bit 2.8V Ind Temp RoHS:否 制造商:STMicroelectronics 監(jiān)測電壓數(shù): 監(jiān)測電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復位:Resettable 監(jiān)視器:No Watchdog 電池備用開關:No Backup 上電復位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
| CAT1024LI-28 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Catalyst Semiconductor 功能描述: |
| CAT1024LI-28-G | 功能描述:監(jiān)控電路 CPU w/2K RoHS:否 制造商:STMicroelectronics 監(jiān)測電壓數(shù): 監(jiān)測電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復位:Resettable 監(jiān)視器:No Watchdog 電池備用開關:No Backup 上電復位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
| CAT1024LI-28-GT2 | 制造商:CATALYST 制造商全稱:Catalyst Semiconductor 功能描述:Supervisory Circuits with I2C Serial 2k-bit CMOS EEPROM and Manual Reset |
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