參數(shù)資料
型號： CA3240E1
元件分類： 通用總線功能
英文描述： 12 STAGE RIPPLE-CARRY BINARY COUNTER/DIVIDERS
中文描述： 集成電路雙運算放大器
文件頁數(shù)： 2/14頁
文件大?。?/td> 342K
代理商： CA3240E1
3-116
Absolute Maximum Ratings
Thermal Information
Supply Voltage (Between V+ and V-) . . . . . . . . . . . . . . . . . . . . . 36V
Differential Input Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8V
Input Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . (V+ +8V) to (V- -0.5V)
Input Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1mA
Output Short Circuit Duration (Note 1) . . . . . . . . . . . . . . . . Indefinite
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40
o
C to 85
o
C
Voltage Range . . . . . . . . . . . . . . . . . . . . . 4V to 36V or
±
2V to
±
18V
Thermal Resistance (Typical, Note 2)
8 Lead PDIP Package . . . . . . . . . . . . . . . . . . . . . . .
14 Lead PDIP Package . . . . . . . . . . . . . . . . . . . . . .
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150
o
C
Maximum Storage Temperature Range . . . . . . . . . -65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300
o
C
θ
JA
(
o
C/W)
100
100
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. Short circuit may be applied to ground or to either supply. Temperatures and/or supply voltages must be limited to keep dissipation within
maximum rating.
2.
θ
JA
is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
For Equipment Design, V
SUPPLY
=
±
15V, T
A
= 25
o
C, Unless Otherwise Specified
PARAMETER
SYMBOL
CA3240
CA3240A
UNITS
MIN
TYP
MAX
MIN
TYP
MAX
Input Offset Voltage
V
IO
I
IO
I
I
A
OL
-
5
15
-
2
5
mV
Input Offset Current
-
0.5
30
-
0.5
20
pA
Input Current
-
10
50
-
10
40
pA
Large-Signal Voltage Gain
(See Figures 13, 28) (Note 3)
20
100
-
20
100
-
kV/V
86
100
-
86
100
-
dB
Common Mode Rejection
Ratio (See Figure 18)
CMRR
-
32
320
-
32
320
μ
V/V
70
90
-
70
90
-
dB
Common Mode Input Voltage
Range (See Figure 25)
V
ICR
-15
-15.5 to
+12.5
11
-15
-15.5 to
+12.5
12
V
Power Supply Rejection Ratio
(See Figure 20)
PSRR
-
100
150
-
100
150
μ
V/V
(
V
IO
/
V
±)
V
OM
+
V
OM
-
V
OM-
I+
76
80
-
76
80
-
dB
Maximum Output Voltage (Note 4)
(See Figures 24, 25)
12
13
-
12
13
-
V
-14
-14.4
-
-14
-14.4
-
V
Maximum Output Voltage (Note 5)
0.4
0.13
-
0.4
0.13
-
V
Total Supply Current
(See Figure 16) For Both Amps
-
8
12
-
8
12
mA
Total Device Dissipation
P
D
-
240
360
-
240
360
mW
NOTES:
3. At V
O
= 26V
P-P
, +12V, -14V and R
L
= 2k
.
4. At R
L
= 2k
.
5. At V+ = 5V, V- = GND, I
SINK
= 200
μ
A.
Electrical Specifications
For Equipment Design, V
SUPPLY
=
±
15V, T
A
= 25
o
C, Unless Otherwise Specified
PARAMETER
SYMBOL
TEST CONDITIONS
TYPICAL VALUES
UNITS
CA3240A CA3240
Input Offset Voltage Adjustment Resistor
(E1 Package Only)
Typical Value of Resistor Between Terminals 4 and
3(5) or Between 4 and 14(8) to Adjust Maximum V
IO
18
4.7
k
Input Resistance
R
I
C
I
R
O
e
N
1.5
1.5
T
Input Capacitance
4
4
pF
Output Resistance
60
60
μ
V
Equivalent Wideband Input Noise Voltage
(See Figure 2)
BW = 140kHz, R
S
= 1M
48
48
CA3240, CA3240A
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