參數(shù)資料
型號(hào)： CA3102E
廠商： INTERSIL CORP
元件分類： 運(yùn)動(dòng)控制電子
英文描述： Dual High Frequency Differential Amplifier For Low Power Applications Up to 500MHz
中文描述： DUAL OP-AMP, 5000 uV OFFSET-MAX, 1350 MHz BAND WIDTH, PDIP14
封裝： PLASTIC, MS-001AA, DIP-14
文件頁數(shù)： 2/11頁
文件大?。?/td> 115K
代理商： CA3102E
2
Absolute Maximum Ratings
Thermal Information
Collector-to-Emitter Voltage, V
CEO
. . . . . . . . . . . . . . . . . . . . . . 15V
Collector-to-Base Voltage, V
CBO
. . . . . . . . . . . . . . . . . . . . . . . . 20V
Collector-to-Substrate Voltage, V
CIO
(Note 1). . . . . . . . . . . . . . 20V
Emitter-to-Base Voltage, V
EBO
. . . . . . . . . . . . . . . . . . . . . . . . . . 5V
Collector Current, I
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA
Operating Conditions
Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . -55
o
C to 125
o
C
Thermal Resistance (Typical, Note 2)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum Power Dissipation (Any One Transistor) . . . . . . . 300mW
Maximum Junction Temperature (Plastic Package) . . . . . . . 150
o
C
Maximum Storage Temperature Range. . . . . . . . . . -65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300
o
C
(SOIC - Lead Tips Only)
θ
JA
(
o
C/W)
110
205
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. The collector of each transistor of the CA3102 is isolated from the substrate by an integral diode. The substrate (Terminal 9) must be connected
to the most negative point in the external circuit to maintain isolation between transistors and to provide for normal transistor action.
2.
θ
JA
is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
T
A
= 25
o
C
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
DC CHARACTERISTICS FOR EACH DIFFERENTIAL AMPLIFIER
Input Offset Voltage (Figures 1, 4)
V
IO
I
IO
I
B
-
0.25
5.0
mV
Input Offset Current (Figure 1)
I
3
= I
9
= 2mA
-
0.3
3.0
μ
A
Input Bias Current (Figures 1, 5)
-
13.5
33
μ
A
Temperature Coefficient
Magnitude of Input Offset Voltage
-
1.1
-
μ
V/
o
C
DC CHARACTERISTICS FOR EACH TRANSISTOR
DC Forward Base-to-Emitter Voltage
(Figure 6)
VBE
V
CE
= 6V, I
C
= 1mA
674
774
874
mV
Temperature Coefficient of
Base-to-Emitter Voltage
(Figure 6)
V
CE
= 6V, I
C
= 1mA
-
-0.9
-
mV/
o
C
Collector Cutoff Current (Figure 7)
I
CBO
V
CB
= 10V, I
E
= 0
I
C
= 1mA, I
B
= 0
I
C
= 10
μ
A, I
E
= 0
I
C
= 10
μ
A, I
B
= I
E
= 0
I
E
= 10
μ
A, I
C
= 0
-
0.0013
100
nA
Collector-to-Emitter Breakdown Voltage
V
(BR)CEO
V
(BR)CBO
V
(BR)CIO
V
(BR)EBO
15
24
-
V
Collector-to-Base Breakdown Voltage
20
60
-
V
Collector-to-Substrate Breakdown Voltage
20
60
-
V
Emitter-to-Base Breakdown Voltage
5
7
-
V
DYNAMIC CHARACTERISTICS FOR EACH DIFFERENTIAL AMPLIFIER
1/f Noise Figure (For Single Transistor)
(Figure 12)
NF
f = 100kHz, R
S
= 500
,
I
C
= 1mA
V
CE
= 6V, I
C
= 5mA
-
1.5
-
dB
Gain Bandwidth Product (For Single
Transistor) (Figure 11)
f
T
-
1.35
-
GHz
Collector-Base Capacitance (Figure 8)
C
CB
I
C
= 0,
V
CB
= 5V
Note 3
-
0.28
-
pF
Note 4
-
0.15
-
pF
Collector-Substrate
Capacitance (Figure 8)
C
CI
I
C
= 0, V
CI
= 5V
-
1.65
-
pF
Common Mode Rejection Ratio
CMRR
I
3
= I
9
= 2mA
Bias Voltage = -6V
-
100
-
dB
AGC Range, One Stage (Figure 2)
AGC
-
75
-
dB
Voltage Gain, Single-Ended Output
(Figures 2, 9, 10)
A
Bias Voltage = -4.2V,
f = 10MHz
18
22
-
dB
V
----------------
V
--------------
CA3102
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